m366s3323dts Samsung Semiconductor, Inc., m366s3323dts Datasheet - Page 10

• Manufacturer Part Number: m366s3323dts
• Description: 32mx64 Sdram Dimm Based On 16mx8, 4banks, 4k Refresh, 3.3v Synchronous Drams With Spd
• Manufacturer: Samsung Semiconductor, Inc.

M366S3323DTS-L7C/L7A/L1H/L1L,C7C/C7A/C1H/C1L (Intel SPD 1.2B ver. base)
M366S3323DTS
Byte #
Organization : 32Mx64
Composition : 16Mx8 *16
Used component part # : K4S280832D-TL7C/TL75/TL1H/TL1L,TC7C/TC75/TC1H/TC1L
# of rows in module : 2 Row
# of banks in component : 4 banks
Feature : 1,375mil height & double sided component
Refresh : 4K/64ms
Contents ;
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuraion type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time from clock @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock @CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
Row
Rows
density
on this assembly
Function Described
banks
RCD
RP
)
)
RAS
on SDRAM device
)
RRD
)
7.5ns
5.4ns
2 & 3
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
15ns
15ns
15ns
45ns
-7C
15.625us, support self refresh
precharge all, auto precharge
Non-buffered, non-registered
Burst Read Single bit Write
+/- 10% voltage tolerance,
& redundant addressing
Function Supported
1, 2, 4, 8 & full page
256bytes (2K-bit)
2
PC133/PC100 Unbuffered DIMM
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
2 & 3
10ns
20ns
15ns
20ns
45ns
t
row
-7A
6ns
CCD
Non parity
128bytes
4
SDRAM
LVTTL
64 bits
0 CLK
0 CLK
2
None
banks
of 128MB
12
10
x8
row
= 1CLK
-
-
-
2 & 3
10ns
10ns
20ns
20ns
20ns
50ns
-1H
6ns
6ns
2ns
1ns
2ns
2 & 3
10ns
12ns
20ns
20ns
20ns
50ns
6ns
7ns
2ns
1ns
2ns
-1L
2Dh
75h
54h
06h
75h
54h
0Fh
0Fh
0Fh
15h
08h
15h
-7C
Rev. 0.1 Sept. 2001
A0h
2Dh
-7A
75h
54h
06h
60h
14h
0Fh
14h
15h
08h
15h
Hex value
0Ch
80h
08h
04h
0Ah
02h
40h
00h
01h
00h
80h
08h
00h
01h
8Fh
04h
01h
01h
00h
0Eh
00h
00h
20h
A0h
A0h
-1H
60h
06h
60h
14h
14h
14h
32h
20h
10h
20h
C0h
A0h
60h
06h
70h
14h
14h
14h
32h
20h
10h
20h
-1L
Note
1
1
2
2
2
2