k4r881869e Samsung Semiconductor, Inc., k4r881869e Datasheet
k4r881869e
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k4r881869e Summary of contents
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... K4R881869E 288Mbit RDRAM 512K x 18bit x 32s banks Direct RDRAM Version 1.4 Dec. 2003 Page -1 Direct RDRAM (E-die) TM Version 1.4 Dec. 2003 ™ ...
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... K4R881869E Change History Version 1.4( Dec. 2003) - First Copy ( Version 1.4x is named to unify the version of component and device operation datasheets) - Based on the 256/288Mb D-die Version 1.4 Direct RDRAM Version 1.4 Dec. 2003 Page 0 ™ ...
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... SAMSUNG SAMSUNG 410 SAMSUNG SAMSUNG 410 SAMSUNG SAMSUNG 410 K4R881869E - K4R881869E - Figure 1: Direct RDRAM CSP Package The 288Mbit RDRAM devices are offered in a CSP hori- zontal package suitable for desktop as well as low-profile add-in card and mobile applications. Key Timing Parameters/Part Numbers ...
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... SAMSUNG SAMSUNG - - K4R881869E K4R881869E The pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 position is marked by the marker . “ ” package are shown in a later section. Refer to Section “Center-Bonded WBGA Package” on page 18. Note - pin # the A1 position. ...
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... K4R881869E Signal I/O Type a SIO1,SIO0 I/O CMOS a CMD I CMOS a SCK I CMOS DDa V CMOS GND GNDa b DQA8..DQA0 I/O RSL b CFM I RSL b CFMN I RSL V REF b CTMN I RSL b CTM I RSL b RQ7..RQ5 or I RSL ROW2..ROW0 b RQ4..RQ0 or I RSL COL4..COL0 b DQB8.. I/O RSL DQB0 Total pin count per package a. All CMOS signals are high-true ...
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... K4R881869E RQ7..RQ5 or DQB8..DQB0 ROW2..ROW0 3 9 1:8 Demux Packet Decode ROWR ROWA ROP Match Mux DM Row Decode PRER ACT Sense Amp 64x72 Internal DQB Data Path Figure 2: 288Mbit (512Kx18x32s) RDRAM Device Block Diagram ...
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... K4R881869E General Description Figure block diagram of the 288Mbit RDRAM device. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types TM of DRAM, and a Direct Rambus interface block which permits an external controller to access this core ...
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... K4R881869E Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 3 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM device ...
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... K4R881869E CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR ROW1 DR4F DR1 BR1 BR4 RsvR ROW0 DR3 DR0 BR2 RsvB AV=1 ROWA Packet CTM/CFM DC4 S=1 COL4 DC3 COL3 DC2 COP1 COL2 DC1 COP0 COL1 DC0 COP2 COL0 COLC Packet ...
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... K4R881869E Field Encoding Summary Table 5 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a ...
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... K4R881869E Table 7 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 18 for a more detailed description ...
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... K4R881869E Electrical Conditions Symbol T Junction temperature under bias Supply voltage DD, DDA V V Supply voltage droop (DC) during NAP interval (t DD,N, DDA Supply voltage ripple (AC) during NAP interval (t DD,N, DDA,N Supply voltage for CMOS pins (2.5V controllers CMOS Supply voltage for CMOS pins (1.8V controllers) ...
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... K4R881869E Electrical Characteristics Symbol Θ Junction-to-Case thermal resistance current @ V REF REF REF,MAX I RSL output high current @ (0≤V OH RSL I current @ RSL I current @ t ALL OL RSL I current @ t OL ∆I RSL I current resolution step Dynamic output impedance @ V OUT RSL I current @ V OL ...
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... K4R881869E Timing Conditions Symbol CTM and CFM cycle times (-1200) t CTM and CFM cycle times (-1066) CYCLE CTM and CFM cycle times (-800) CTM and CFM input rise and fall times. Use the minimum value of these parameters during testing. (-1200 CTM and CFM input rise and fall times ...
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... K4R881869E Symbol t SIO0 setup time to SCK falling edge S2 t SIO0 hold time to SCK falling edge H2 t PDEV setup time on DQA5..0 to SCK rising edge PDEV hold time on DQA5..0 to SCK rising edge ROW2..0, COL4..0 setup time for quiet window ...
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... K4R881869E Timing Characteristics Symbol CTM-to-DQA/DQB output time @ t t CTM-to-DQA/DQB output time @ t Q CTM-to-DQA/DQB output time @ t DQA/DQB output rise and fall times @ DQA/DQB output rise and fall times @ DQA/DQB output rise and fall times @ t t SCK(neg)-to-SIO0 delay @ C ...
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... K4R881869E Timing Parameters Parameter Row Cycle time of RDRAM banks -the interval between ROWA packets with t RC ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with t ACT command and next ROWR packet with PRER RAS bank. ...
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... K4R881869E Absolute Maximum Ratings Symbol V Voltage applied to any RSL or CMOS pin with respect to Gnd I,ABS Voltage on VDD and VDDA with respect to Gnd DD,ABS DDA,ABS T Storage temperature STORE T Minimum operation temperature MIN Θ Note*) Component : refer to T Module: refre ...
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... K4R881869E Capacitance and Inductance Symbol Parameter and Conditions - RSL pins RSL effective input inductance L RSL effective input inductance I RSL effective input inductance Mutual inductance between any DQA or DQB RSL signals Mutual inductance between any ROW or COL RSL signals. ∆L Difference in L value between any RSL pins of a single device ...
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... K4R881869E Center-Bonded WBGA Package (92balls) Figure 4 shows the form and dimensions of the recom- mended package for the 92balls center-bonded WBGA device class Figure 4: Center-Bonded WBGA Package Table lists the numerical values corresponding to dimen- sions shown in Figure 4 ...