w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 49

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

Base Address register.
EEPROM waveform and timing and can read, write or erase the EEPROM's content.
7.9.2 8-bit Microprocessor Interface
operation modes: clock for PCI mode, HIGH for Intel bus mode, LOW for Motorola bus mode.
7.10 Peripheral Control
W6692, therefore eliminates the need for another PCI controller chip. The peripheral control function includes timer, interrupt
inputs and programmable IOs or microprocessor interface.
the cadence of ring tone. TIMR2 is a short period timer which can be used to generate the 20 Hz ring signal.
interrupt is generated which in turn will make an interrupt request on PCI bus if it is unmasked. The interrupt status bits are
ISTA:XINT0, ISTA:XINT1. The mask bits are IMASK:XINT0, IMASK:XINT1. In addition, the signal level can be read at bits
SQR:XIND0, SQR;XIND1. These pins can be used for monitor of SLIC hook state and/or DTMF data valid status.
The Address Register Control determines the PCI address register's implementation. Bit 13 is the prefetchable bit in Memory
In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be directly controlled by
There are two interrupt inputpins : XINTIN0, XINTIN1. Whenever signal level changes (eith rising or falling), a maskable
Word 6 (Bytes 12,13) is for Address Register Control, its format is :
In all cases, Memory Base Address register allocates 4096 byte spaces and IO Base Address register allocates 256 byte space.
Word 7 is Power Management Capability register. It replaces the chip's default value if EEPROM is not empty.
W6692 provides an EPCTL register for on-board access of the serial EEPROM. Software is responsible for creation of the serial
At power up, the reset pin RST# must be asserted to initialize the chip. At rising edge of RST#, data at CLK pin determines the
There are two timers implemented in W6692: TIMR1 and TIMR2. TIMR1 is a long period timer whcich can be used to control
TIMR1
TIMR2
MEN
EEPROM empty
MEN
1
1
0
0
15
IEN
IEN
14
Address
10H
4CH
1
0
1
0
PRE
13
PCI Configuration Space
Location 10H
Memory Base Address Reg.
Memory Base Address Reg.
IO Base Address Reg.
Not Implemented
Memory Base Address Reg.
Interrupt status
DEXIR:T1EXP
DEXIR:TIN2
12
Interrupt mask
DEXIM:T1EXP
DEXIM:TIN2
not used
PCI Configuration Space
Location 14H
IO Base Address Reg.
Not Implemented
Not Implemented
Not Implemented
IO Base Address Reg.
-49 -
Output pin
No
TOUT2
Period
(0..127)x 100 ms
(1..63) ms
W6692 PCI ISDN S/T-Controller
0
Publication Release Date:
PRE=0
Bit 13
used ?
yes
yes
no
no
Preliminary Data Sheet
Cyclic
yes (CNT=7)
yes(TMD=1)
Sep 30, 1999
Revision 0.9