at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet - Page 28

• Manufacturer Part Number: at572d940hf-cl
• Description: Diopsis 940hf Arm926ej-s Plus Gflops
• Manufacturer: ATMEL Corporation

5.11.2
Table 5-6.
28
PIO A [016
PIO A [10]
PIO A [11]
PIO A [12]
PIO A [13]
PIO A [14]
PIO A [15]
PIO A [17]
PIO A [18]
PIO A [19]
PIO A [20]
PIO A [21]
PIO A [22]
PIO A [0]
PIO A [1]
PIO A [2]
PIO A [3]
PIO A [4]
PIO A [5]
PIO A [6]
PIO A [7]
PIO A [8]
PIO A [9]
PIO A
AT572D940HF Preliminary
Peripheral Multiplexing
PIO A Line Resource Mapping
AIC input: EXT_IRQ1
USART 0 input: RXD
USART 0 input: CTS
ETH input: EREFCK
ETH input: ECRSDV
ETH input: ERXER
ETH input: ERX0
ETH input: ERX1
Periph INPUT A
(also to mAgicV)
Table 5-5.
The D940HF features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines
of the peripheral set. Each PIO controller manages up to thirty-two lines. Each line can be
assigned to one of the two peripheral functions, A or B.
lines of the peripherals A and B are multiplexed on the PIO Controllers. Note that some output
only peripheral functions might be duplicated within the tables and are indicated with the suffix II
and III.
USART 0 bidir: TXD
USART 0 bidir: SCK
SPI 0 bidir: MISO
SPI 0 bidir: MOSI
SPI 0 bidir: CLK
SPI 0 bidir: CS0
ETH bidir MDIO
Peripheral ID
29
30
31
Peripheral ID (Continued)
USART 0 output: RTS
ETH output: FCE100
Periph OUTPUT A
ETH output: ETX0
ETH output: ETX1
SPI 0 output: CS1
SPI 0 output: CS2
SPI 0 output: CS3
ETH output MDC
Peripheral Clock Assignment
TIMER input: TIMER_IN 1
TIMER input: TIMER_IN 2
AIC input: EXT_IRQ2
Periph INPUT B
(also to mAgicV)
TIMER bidir: TIMER_OUT A0
TIMER bidir: TIMER_OUT B1
Table 5-6
to
EBI: output: NCS4/CFCS0 (III)
EBI: output: NCS5/CFCS1 (III)
Table 5-8
USART 0 output: RTS (III)
mAgicV output: M_SIRQ0
mAgicV output: M_SIRQ2
mAgicV output: M_SIRQ1
Host Clock Assignment
DBGU output: DTXD(III)
EBI: output: CFCE1 (III)
EBI: output: CFCE2 (III)
PMC output: CKOUT 1
PMC output: CKOUT 0
EBI: output: NCS6 (III)
EBI: output: NCS7 (III)
SPI 0 output: CS1 (III)
SPI 0 output: CS2 (III)
TEST output: m_ck
Periph OUTPUT B
TEST output: a_ck
CAN 1: dout (III)
define how the I/O
7010AS–DSP–07/07