at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet - Page 4

• Manufacturer Part Number: at572d940hf-cl
• Description: Diopsis 940hf Arm926ej-s Plus Gflops
• Manufacturer: ATMEL Corporation

1. Description
DIOPSIS 940HF is a Dual CPU Processor integrating a mAgicV VLIW DSP and an ARM926EJ-
S RISC MCU, plus a total of 370 Kbytes SRAM. The system combines the flexibility of the
™
ARM926
RISC controller with the very high performance of the DSP.
mAgicV is a high performance VLIW DSP of the Magic DSP family, delivering 1 Giga floating-
point operations per second (GFLOPS) and 1.6 Gops at a clock rate of 100 MHz. It is equipped
with an AHB master port and an AHB slave port for system-on-chip integration. It has 256 data
registers, 64 address registers, 10 independent arithmetic operating units, 2 independent
address generation units and a DMA engine. To sustain the internal parallelism, the data band-
width among the Register File, the Operators and the Data Memory System, is 80 bytes/cycle.
The Data Memory System is designed to transfer 28 bytes/cycle. For instance, mAgicV can pro-
duce one complete FFT butterfly per cycle by activating all the computing units. mAgicV
operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format
for numerical computations, while internal memory accesses are supported by a powerful 16-bit
MAGU (Multiple Address Generation Unit). It has also on-chip 16K x 40-bit 6-access/cycle data
memory system and 8K x 128-bit dual port program memory locations. Efficient usage of the
internal program memory is achieved through a general purpose code compression mechanism
and software pipelining support of systematic loops.
A C-oriented architecture and an optimizing assembler ease the user from the burden of dealing
with the parallelism of the processor resources and significantly simplifies the code develop-
ment. A rich library of C-callable DSP routines is available.
The ARM926 embedded micro controller core is a member of the Advanced RISC Machines
(ARM) family of general purpose 32-bit microprocessors, which offer high performance and very
low power consumption. The ARM architecture is based on Reduced Instruction Set Computer
(RISC) principles, and the instruction set and the related decode mechanism are much simpler
than the micro programmed Complex Instruction Set Computers.
This simplicity results in a high instruction throughput and impressive real-time interrupt
response. The ARM926 supports 16-bit Thumb subset of the most commonly used 32-bit
instructions. These are expanded at run time with no degradation of the system performance.
This gives 16-bit code density (saving memory area and cost) coupled with a 32-bit processor
performance.
A rich set of peripherals and a 48 Kbytes internal memory provide a highly flexible and inte-
grated system solution.
The ARM926EJ-S supports the Jazelle technology for Java acceleration.
AT572D940HF Preliminary
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7010AS–DSP–07/07