as4c256k16fo Alliance Memory, Inc, as4c256k16fo Datasheet - Page 6

• Manufacturer Part Number: as4c256k16fo
• Description: 5v 256k X 16 Cmos Dram Fast Page Mode
• Manufacturer: Alliance Memory, Inc

Refresh cycle
Output enable
Self refresh cycle
Notes
1
2
3
4
5
6
7
8
9
10 t
11 t
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
14 t
15 These parameters are sampled, but not 100% tested.
Standard
Standard
Standard
Symbol
Symbol
Symbol
t
4/11/01; V.0.9.1
t
t
t
t
t
t
t
t
t
t
t
RASS
CHS
I
I
An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
AC characteristics assume t
V
V
Operation within the t
fied t
Operation within the t
fied t
Assumes three state test load (5 pF and a 380
Either t
t
neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
CHR
ROH
OED
OEH
RPS
OEA
OEZ
CSR
RPC
CPT
CC1
CC1
OFF
WCS
WS
ASC
CC
IH
t
RWD
.
, I
(min) and V
(min) and t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
, t
and I
RCD
RAD
CC3
WCH
t
RCH
CP
(min), t
RAS pulse width (CBR self refresh)
RAS precharge time (CBR self refresh)
CAS hold time (CBR self refresh)
(max) limit, then access time is controlled exclusively by t
(max) limit, then access time is controlled exclusively by t
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
CAS precharge time
(CAS-before-RAS counter test)
RAS hold time referenced to OE
OE access time
OE to data delay
Output buffer turnoff delay from OE
OE command hold time
, I
CC4
to achieve t
, t
or t
CC4
RWD
depend on output loading. Specified values are obtained with the output open.
, and I
RRH
WH
CWD
IL
, t
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
CWD
must be satisfied for a read cycle.
CC6
PC
t
RCD
RAD
WH
t
CWD
and t
(min) and t
depend on cycle rate.
Parameter
Parameter
T
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
Parameter
(max) limit insures that t
(max) limit insures that t
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V
(min) and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
CAP
(max) values.
AWD
CAA
t
AWD
Thevenin equivalent).
or t
RAC
RAC
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If
CAC
Alliance Semiconductor
(max) can be met. t
(max) can be met. t
or t
100K
Min
Min
Min
10
85
30
7
0
8
CAP
5
–
5
–
5
.
–25
–25
–25
CAC
AA
Max
Max
Max
.
–
–
–
–
–
–
–
–
8
–
6
–
.
(V
(V
(V
RCD
RAD
CC
CC
CC
100K
Min
Min
Min
10
85
30
7
0
8
5
–
5
–
8
®
(max) is specified as a reference point only. If t
(max) is specified as a reference point only. If t
= 5V ± 10%, GND = 0V, T
= 5V ± 10%, GND = 0V, T
= 5V ± 10%, GND = 0V, T
–30
–30
–30
Max
Max
Max
10
–
–
–
–
–
–
8
–
–
–
–
100K
Min
Min
Min
10
85
30
8
0
8
5
–
5
–
8
–35
–35
–35
Max
Max
Max
10
–
–
8
–
–
–
–
–
–
–
–
Min
100K
Min
Min
10
10
5
–
8
–
8
85
30
0
8
–50
–50
–50
IL
Max
a
Max
a
a
10
Max
(min)
–
–
8
–
–
–
–
–
= 0 C to +70 C)
= 0 C to +70 C
= 0 C to +70 C
IH
–
–
–
AS4C256K16FO
RCD
RAD
and V
is greater than the speci-
is greater than the speci-
Unit
Unit
GND and V
Unit
IL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.
P. 6 of 25
Notes
Notes
WS
Notes
IH
8
3
3
(max)
RWD
)
)