adv476 Analog Devices, Inc., adv476 Datasheet - Page 6

• Manufacturer Part Number: adv476
• Description: Cmos Monolithic 256x18 Color Palette Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV476
MPU Interface
As illustrated in the functional block diagram, the ADV476 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM.
The RS0 and RS1 control inputs specify whether the MPU is
accessing the address register or the color palette RAM, as
shown in Table I. The 8-bit address register is used to address
the color palette RAM, eliminating the requirement for external
address multiplexers.
RS1
0
1
0
1
To write color data, the MPU writes to the address register with
the 8-bit address of the color palette RAM location which is to
be modified. The MPU performs three successive write cycles
(six bits of red data, six bits of green data and six bits of blue
data). During the blue write cycle, the three bytes of color infor-
mation are concatenated into an 18-bit word and written to the
location specified by the address register. The address register
then automatically increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
To read back color data, the MPU loads the address register
with the address of the color palette RAM location to be read.
The MPU performs three successive read cycles (6 bits each of
red, green and blue data). Following the blue read cycle, the
RD
1
1
1
1
0
0
0
0
0
RS0
0
1
1
0
Table I. Control Input Truth Table
WR
0
0
0
0
1
1
1
1
0
Addressed by MPU
Pixel Address Register (RAM Write Mode)
Pixel Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
ADDRa,b (Counts Modulo 3)
ADDR0–7 (Counts Binary)
RS0
0
1
1
1
1
1
1
1
X
RS1
0
0
0
0
1
0
0
0
X
Table III. Truth Table for Read/Write Operations
Table II. Address Register (ADDR) Operation
ADDRa
X
0
0
1
X
0
0
1
X
Value
00
01
10
00H–FFH
ADDRb
X
0
1
0
X
0
1
0
X
–6–
address register increments to the next location which the MPU
may read by simply reading another sequence of red, green and
blue data.
This 6-bit color data is right justified, i.e., the lower six bits of
the data bus with D0 being the LSB and D5 the MSB. D6 and
D7 are ignored during a color write cycle and are set to zero
during a color read cycle.
During color palette RAM access, the address register resets to
00H following a blue read or write operation to RAM location
FFH.
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color
registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the period between MPU accesses.
Color (RGB) data is normally loaded to the color palette RAM
during video screen retrace, i.e., during the video waveform
blanking period, see Figure 5.
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR0–7) are accessible to the MPU, and are used to
address color palette RAM locations, as shown in Table III.
ADDR0 is the LSB when the MPU is accessing the RAM. The
MPU may read the address register at any time without modify-
ing its contents or the existing read/write mode.
Figure 1 illustrates the MPU read/write timing and Table III
shows the associated functional instructions.
RS1
0
Operation Performed
Write Address Register;
Write Red Value;
Write Green Value;
Write Blue Value;
Read Address Register;
Read Red Value;
Read Green Value;
Read Blue Value;
Invalid Operation
RS0
1
Addressed by MPU
Red Value
Green Value
Blue Value
Color Palette RAM
D0–D7 ADDR0–7
0 ADDRa,b
Increment ADDRa–b
Increment ADDRa–b
Modify RAM Location
Increment ADDR0–7
Increment ADDRa–b
ADDR0–7 D0–D7
Increment ADDRa–b
Increment ADDRa–b
Increment ADDR0–7
Increment ADDRa–b
REV. B