adv476 Analog Devices, Inc., adv476 Datasheet - Page 9

• Manufacturer Part Number: adv476
• Description: Cmos Monolithic 256x18 Color Palette Ram-dac
• Manufacturer: Analog Devices, Inc.

REV. B
PC BOARD LAYOUT CONSIDERATIONS
The ADV476 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. For optimum sys-
tem noise performance, it is imperative that great care be given
to the PC board layout. The layout should be optimized for low-
est noise on the ADV476 power and ground lines. This can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of V
pins should by minimized so as to minimize inductive ringing.
Ground Planes
The ground plane should encompass all ADV476 ground pins,
voltage reference circuitry, power supply bypass circuitry, the
analog output traces and all the digital signal traces leading up
to the ADV476.
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane (V
ciated analog circuitry. This power plane should be connected
to the regular PCB power plane at a single point through a fer-
rite bead, as illustrated in Figure 7. This bead should be located
within three inches of the ADV476.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV476 power pins, current reference circuitry
and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors, see Figure 7.
Optimum performance is achieved by the use of 0.1 F ceramic
capacitors. This should be done by placing the capacitors as
close as possible to the device with the capacitor leads as short
as possible, thus minimizing lead inductance.
CC
) should encompass the ADV476 and all asso-
CC
and GND
–9–
It is important to note that while the ADV476 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV476 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
Due to the high clock rates used, long clock lines to the
ADV476 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane and not
the analog power plane.
Analog Signal Interconnect
The ADV476 should be located as close as possible to the out-
put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 . This termi-
nation resistance should be as close as possible to the ADV476
to minimize reflections.
Note: For additional information on PC Board-Layout see
Application Note “Design and Layout of a Video Graphics
System for Reduced EMI”, available from Analog Devices
(Pub. No. E1309–15–10/89).
ADV476