msm5416282 Oki Semiconductor, msm5416282 Datasheet - Page 9

• Manufacturer Part Number: msm5416282
• Description: Msm5416282256k X 16 Vram Fpm 2we
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Notes:
10. t
11. Either t
12. These parameters are referenced to CAS leading edge of early write cycles, and to
13. t
14. Operation within the t
15. Operation within the t
16. Input levels at the AC testing are 3.0 V/0 V.
17. Address (A0 - A8) may be changed two times or less while RAS = V
18. Address (A0 - A8) may be changed once or less while CAS = V
19. This is guaranteed by design. (t
1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage
2. All voltages are referenced to V
3. These parameters depend on the cycle rate.
4. These parameters depend on output loading. Specified values are obtained with the
5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles
6. AC measurements assume t
7. V
8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.
9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
to the device.
output open.
(TRG = "high") and any 8 SC cycles before proper device operation is achieved.
In the case of using an internal refresh counter, a minimum of 8 CAS before RAS
cycles instead of 8 RAS cycles are required.
Also, transition times are measured between V
DOUT reference levels : V
DOUT reference levels : V
outputs achieve the open circuit condition, and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
WE leading edge in TRG controlled write cycles and read modify write cycles.
They are included in the data sheet as electrical characteristics only.
If t
remain open circuit throughout the entire cycle; If t
(Min.) and t
out will contain data read from the selected cell; If neither of the above sets of
conditions are satisfied, the condition of the data out is indeterminate.
t
t
(Max.) is specified as a reference point only: If t
(Max.) limit, then access time is controlled by t
This parameter is not 100% tested.
RCD
OFF
WCS
RCD
IH
WCS
(Min.) and V
(Max.), t
, t
(Max.) is specified as a reference point only: If t
(Max.) limit, then access time is controlled by t
RWD
RCH
t
WCS
, t
AWD
or t
CWD
OEZ
(Min.), the cycle is an early write cycle, and the data out pin will
RRH
IL
(Max.), t
and t
t
(Max.) are reference levels for measuring timing of input signals.
AWD
must be satisfied for a read cycle.
RCD
RAD
AWD
(Min.), the cycle is a read modify write cycle, and the data
SDZ
OH
OH
(Max.) limit ensures that t
(Max.) limit ensures that t
T
are not restrictive operating parameters.
/V
/V
= 5 ns.
(Max.) and t
SOH
SS
OL
OL
.
= 2.0 V/0.8 V.
= 2.0 V/0.8 V.
/t
COH
SEZ
= t
RAD
SCA
(Max.) define the time at which the
IH
AA
/t
is greater than the specified t
and V
RWD
.
RCD
CAC
CAC
RAC
RAC
is greater than the specified
- output transition time)
IL
.
t
RWD
.
(Max.) can be met.
(Max.) can be met. t
(Min.), t
FEDS5416282-05
IH
and RAS = V
MSM5416282
IL
CWD
.
t
9/38
CWD
RAD
RAD
IL
.