s5920 Applied Micro Circuits Corporation (AMCC), s5920 Datasheet - Page 104

• Manufacturer Part Number: s5920
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5920 – PCI Product: PCI Bus Protocol
PCI READ TRANSFERS
The S5920 responds to PCI bus memory or I/O read
transfers when it is selected as a target.
PCI targets may drive DEVSEL# and TRDY# after the
end of the address phase. TRDY# is not driven until
the target can provide valid data for the PCI read.
Read accesses from the S5920 operation registers
are shown in Figure 1. The S5920 conditionally
asserts STOP# in clock period 3 if the initiator keeps
FRAME# asserted during clock period 2 with IRDY#
asserted (indicating a burst is being attempted). Wait
states may be added by the initiator by not asserting
the signal IRDY# during clock 3 and beyond. If
F R A M E # r e m a i n s a s s e r t e d , b u t I R D Y # i s n o t
asserted, the initiator is just adding wait states, not
necessarily attempting a burst.
Figure 45. Single Data Phase PCI Bus Read of S5920
There are only two conditions where accesses to the
S5920 do not return TRDY#, but assert STOP#
instead. This condition is called a target-initiated termi-
nation or target disconnect. This can occur when a
read attempt is made to an empty Pass-Thru FIFO.
The second condition may occur when read accesses
to the expansion ROM generate a retry if the nvRAM
interface has not finished reading 4 bytes.
When burst read transfers are attempted to the S5920
operation registers, configuration registers or expan-
sion ROM, STOP# is asserted during the first data
transfer to indicate to the initiator that no further trans-
fers (data phases) are possible. This is a target-
initiated termination where the target disconnects after
AMCC Confidential and Proprietary
C/BE[3:0]#
PCLK
FRAME#
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
Registers or Expansion ROM
(I)
12345
Bus Cmd
Address
Byte Enables
(T)
Data
(I) Driven by Initiator
(T) Driven by Target
the first data phase. Figure 2 shows the signal relation-
ships during a burst read attempt to the S5920
operation registers.
PCI WRITE TRANSFERS
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases.
Write accesses to the S5920 operation registers are
shown in Figure 3. Here, the S5920 asserts the signal
STOP# in clock period 3. STOP# is asserted because
the S5920 does not support burst writes to operation
registers. Wait states may be added by the initiator by
not asserting the signal IRDY# during clock 2 and
beyond. There is only one condition where writes to
S5920 internal registers do not return TRDY# (but do
assert STOP#). This is called a target-initiated termi-
nation or target disconnect. This occurs when a write
attempt is made to a full Pass-Thru FIFO. The asser-
tion of STOP# without the assertion of TRDY#
indicates that the initiator should retry the operation
later. The S5920 will sustain a burst as long as the
FIFO is not full.
Figure 46. Burst PCI Bus Read Attempt to S5920 Reg-
C/BE[3:0]#
PCLK
FRAME#
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
isters or Expansion ROM
(I)
Bus Cmd
12345
Address
Revision 1.02 – April 12, 2007
Byte Enables
(T)
Data
Data Book
(I) Driven by Initiator
(T) Driven by Target
DS1596
104