s5920 Applied Micro Circuits Corporation (AMCC), s5920 Datasheet - Page 139
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s5920
Manufacturer Part Number
s5920
Description
Pci Product
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.S5920.pdf
(165 pages)
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S5920 – PCI Product: Pass-Thru Operation
Table 57. Big Endian conversion for a 16-bit bus. The
S5920 drives D[15:0] only
Table 58. Big Endian conversion for an 8-bit bus. The
S5920 drives D[7:0] only
In Active mode, wait states can also be programmed.
This enables easier interfacing to slow Add-On logic
which cannot transfer data at the full ADCLK-
speed.The S5920 inserts a turnaround cycle after the
address phase for PCI Read cycles. If one or more
wait states have been programmed, the turnaround
cycle is considered the first wait state of the first data
phase of that transaction.
For all Active mode transfers, the DXFR# signal is
used by Add-On logic as the data transfer signal. Data
must be latched at the rising edge of ADCLK when
DXFR# is asserted for a PCI write. Conversely, for PCI
Reads, the rising edge of ADCLK when DXFR# is
asserted can be used to increment to the next data
field.
AMCC Confidential and Proprietary
2nd XFER
2nd XFER
2nd XFER
1st XFER
1st XFER
1st XFER
3rd XFER
4th XFER
Transfer
Transfer
Byte #
Byte #
0
1
2
3
0
1
2
3
PCI Byte
D23-D16
D31-D24
PCI Byte
D23-D16
D31-D24
D15-D8
D15-D8
D7-D0
D7-D0
Lane
Lane
Add-On Bus
Add-On Bus
Byte Lane
Byte Lane
D7-D0
D7-D0
D7-D0
D7-D0
D15-D8
D15-D8
D7-D0
D7-D0
Figure 71. Active mode PCI Read (Zero Programmed
Figure 72. Active Mode PCI Read without PTADR#
The PTADR# signal is controlled by the most signifi-
cant bit of every region control field in the PTCR
register. If this bit is zero then the PTADR# pin is not
driven at the start of an Active mode transfer. If this bit
is set to one, the PTADR# pin will be enabled and
driven active (low) for one and only one clock after
PTATN# was sampled active provided PTWAIT# was
also sampled high.
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]
DXFR#
DQ[31:0]
PTWAIT#
PTADR#
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]
DXFR#
DQ[31:0]
PTWAIT#
PTADR#
ADCLK
ADCLK
Wait States) with PTADR#
1
1
2
2
01b
0h
PTADDR
DATA
Revision 1.02 – April 12, 2007
0h
3
3
01b
Fh
4
4
DATA
Data Book
5
5
Fh
DS1596
6
6
7
7
139
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