w49v002a Winbond Electronics Corp America, w49v002a Datasheet - Page 21

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w49v002a

Manufacturer Part Number
w49v002a
Description
256k X 8 Cmos Flash Memory With Lpc Interface
Manufacturer
Winbond Electronics Corp America
Datasheet

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LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
AC Test Load and Waveform
Read/Write Cycle Timing Parameters
(V
Reset Timing Parameters
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
Vdd stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
Reset Active to Output Float
Reset Inactive to Input Active
Clock Cycle Time
Input Set Up Time
Input Hold Time
Clock to Data Valid
Input Pulse Levels
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
DD
= 3.3V
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
D
Test when output from low to high
OUT
10 pF
5%, V
PARAMETER
PARAMETER
PARAMETER
GND
= 0V, T
A
25
= 0 to 70 C)
D
Test when output from high to low
OUT
10 pF
SYM.
T
T
T
T
CYC
0.6 V
1 V/nS
0.4V
1 TTL Gate and C
HD
SU
KQ
SYMBOL
DD
T
T
T
T
T
DD
25
- 21 -
PRST
KRST
RSTP
RSTF
RST
/ 0.4V
to 0.2 V
V
DD
DD
MIN.
30
7
0
-
Preliminary W49V002A
DD
L
= 10 pF
0.6V
0.2V
W49V002A
MIN.
100
100
1
1
-
CONDITIONS
DD
DD
Publication Release Date: April 2001
Input
Test Point
TYP.
MAX.
11
0.4V
-
-
-
-
-
-
-
-
DD
Output
Test Point
MAX.
50
-
-
-
-
0.4V
DD
Revision A1
UNIT
nS
nS
nS
nS
UNIT
mS
nS
nS
S
S

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