gal6002 Lattice Semiconductor Corp., gal6002 Datasheet

no-image

gal6002

Manufacturer Part Number
gal6002
Description
High Performance E2 Cmos Fpla Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
gal6002B-15LJ
Manufacturer:
LATTICE
Quantity:
1 200
Part Number:
gal6002B-15LJ
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
gal6002B-15LP
Manufacturer:
MIT
Quantity:
6 243
Part Number:
gal6002B-15LP
Manufacturer:
LATTICE
Quantity:
3 021
Part Number:
gal6002B-20LJ
Manufacturer:
LATTICE
Quantity:
3 444
Part Number:
gal6002B-20LJ
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
gal6002B-20LP
Manufacturer:
NXP
Quantity:
829
• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
• E
• UNPRECEDENTED FUNCTIONAL DENSITY
• HIGH-LEVEL DESIGN FLEXIBILITY
• APPLICATIONS INCLUDE:
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6002_02
Features
Description
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
— 90mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
2
CELL TECHNOLOGY
and FPLA Devices
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
CMOS technology offers
®
1
Functional Block Diagram
Macrocell Names
PinNames
Pin Configuration
ILMC
IOLMC I/O LOGIC MACROCELL
BLMC
OLMC
I
ICLK
OCLK
INPUTS
0
2-11
CLOCK
- I
INPUT
NC
10
I
I
I
I
I
I
{
11
5
7
9
12
4
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
INPUT
INPUT CLOCK
OUTPUT CLOCK
2
GAL6002
11
Top View
ILMC
0
14
PLCC
2
7
BLMC
High Performance E
ICLK
28
16
D
E
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
AND
OR
Generic Array Logic™
I/O/Q
V
GND
CC
GAL6002
D
E
OUTPUT
ENABLE
14
I/ICLK
BIDIRECTIONAL
POWER (+5V)
GROUND
GND
23
OLMC
I
I
I
I
I
I
I
I
I
I
2
OCLK
CMOS FPLA
1
12
6
6002
GAL
DIP
14
23
IOLMC
July 1997
18
24
13
{
OUTPUTS
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK
OUTPUT
14 - 23
CLOCK

Related parts for gal6002

gal6002 Summary of contents

Page 1

... Multiple PLD Device Integration Description Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently ...

Page 2

... GAL6002 Commercial Device Ordering Information Commercial Grade Specifications Part Number Description GAL6002B Device Name Speed (ns Low Power Power ...

Page 3

... Individually configurable inputs provide system designers with unparalleled design flexibility. With the GAL6002, external input registers and latches are not necessary. Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC) The outputs of the OR array feed two groups of macrocells. One group of eight macrocells is buried ...

Page 4

... Q D INVALID REG LATCH(i) ILMC/IOLMC Generic Logic Block Diagram I/O Macrocell JEDEC Fuse Numbers IOSYNC 8238 8240 8242 8244 8246 8248 8250 8252 8254 8256 4 Specifications GAL6002 MUX AND ARRAY ISYN(i) IOLATCH IOLMC 8239 9 8241 8 8243 7 8245 ...

Page 5

... Specifications GAL6002 OE PRODUCT TERM AND IOLMC ARRAY MUX 1 I/O 0 OLMC ONLY OSYN(i) CKS OUTSYNC 8175 8176 8172 8173 8169 8170 8166 8167 8163 8164 ...

Page 6

... Logic Diagram Specifications GAL6002 6 ...

Page 7

... Logic Diagram (Continued) Specifications GAL6002 7 ...

Page 8

... MAX. Vin = MAX. Vin = 0. OUT = 0. 3. 15MHz Outputs Open = MAXIMUM Specifications GAL6002 ) ............................... MIN. TYP. 3 MAX. — Vss – 0.5 2.0 — Vcc+1 — — -100 — — — — IH 2.4 — IH — ...

Page 9

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Over Recommended Operating Conditions t t su3+ co3 su4+ co4 su3+ cf1 su4+ cf2) 9 Specifications GAL6002 COM COM -15 -20 MIN. MAX. MIN. MAX. — 15 — 20 — 15 — 20 — 18 — 23 — ...

Page 10

... Input or I/O to Asynchronous Reg. Reset t arr1 — Asynchronous Reset to OCLK Recovery Time t arr2 — Asynchronous Reset to Sum Term CLK Recovery Time 1) Refer to Switching Test Conditions section. Over Recommended Operating Conditions 10 Specifications GAL6002 COM COM -15 -20 MIN. MAX. MIN. MAX. 6 — 7 — 6 — ...

Page 11

... I/O FEEDBACK t OCLK h4 t co4 REGISTERED OUTPUT max2 INPUT or I/O FEEDBACK t DRIVING AR en REGISTERED OUTPUT Sum Term CLK t wl1,2 OCLK t wl3 11 Specifications GAL6002 VALID INPUT t t su2 h2 t co2 t su5 t su6 Registered Input VALID INPUT t t su3 h3 t co3 f 1/ max1 Registered Output (OCLK) ...

Page 12

... See Figure FROM OUTPUT (O/Q) UNDER TEST 390 50pF 390 50pF *C 390 50pF 390 5pF 390 5pF 12 Specifications GAL6002 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + INCLUDES TEST FIXTURE AND PROBE CAPACITANCE ...

Page 13

... Then the machine can be sequenced and the outputs tested for correct next state generation. All of the registers in the GAL6002 can be preloaded, including the ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con- tents of the state and output registers can be examined in a special diagnostics mode ...

Page 14

... Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL6002 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr MAX result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins ...

Page 15

... Number of Outputs Switching Delta Tco vs Output Loading 12 10 RISE 8 FALL 150 200 250 300 Output Loading (pF) 15 Specifications GAL6002 Normalized Tsu vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.50 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 125 -55 - Temperature (deg. C) ...

Page 16

... Vin (V) Voh vs Ioh 80.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 0.7 5.50 -55 - Temperature (deg. C) Input Clamp (Vik 100 -2.00 -1.50 -1.00 -0.50 Vik (V) 16 Specifications GAL6002 Voh vs Ioh 4.5 4.25 4 3.75 3.5 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) 0.00 3.00 4.00 75 100 ...

Related keywords