k7r321882m Samsung Semiconductor, Inc., k7r321882m Datasheet - Page 4

• Manufacturer Part Number: k7r321882m
• Description: 1mx36-bit, 2mx18-bit, 4mx9-bit Qdrtm Ii B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R323682M
K7R321882M
K7R320982M
PIN CONFIGURATIONS
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
B W
SYMBOL
G
M
CQ, C Q
A
B
C
D
E
F
H
K
L
N
P
R
J
Q0-17
D0-17
V
V
TMS
TDO
K, K
C, C
TCK
Doff
V
V
2. When ZQ pin is directly connected to V
2. BW
TDI
SA
0
ZQ
NC
W
DDQ
3. Not connected to chip pad internally.
R
REF
, BW
DD
SS
0
1
TDO
Doff
C Q
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
controls write to D0:D8 and BW
1
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
V
10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M,
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
SS
V
Q12
Q15
TCK
D11
D13
D17
Q9
NC
NC
NC
NC
NC
NC
REF
2
/SA*
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
V
(TOP VIEW) K7R321882M(2Mx18)
Q10
Q11
Q13
Q14
Q16
Q17
D10
D12
D14
D15
D16
SA
SA
D9
DDQ
9M,1N,9N,10N,1P,2P,9P
3
R E F
3F,2G,3J,3L,3M,2N
2F,3G,3K,2L,3N,3P
voltage.
PIN NUMBERS
1
D D
controls write to D9:D17.
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
11A, 1A
2H,10H
6P, 6R
6B, 6A
7B, 5A
V
V
V
V
V
V
V
V
V
V
V
SA
SA
SA
11H
10R
11R
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1H
4A
8A
2R
1R
4
SS
SS
SS
SS
1Mx36 & 2Mx18 & 4Mx9 QDR
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
1
- 4 -
V
V
V
V
V
V
V
V
V
SA
SA
C
C
6
K
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
7
SS
SS
DD
DD
DD
DD
DD
SS
SS
0
Block Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Read Control Pin,active when low
Write Control Pin,active when low
Input Clock for Output Data
V
V
V
V
V
V
V
Input Reference Voltage
V
V
V
V
JTAG Test Mode Select
JTAG Test Data Output
SA
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DLL Disable when low
Power Supply ( 1.8 V )
R
JTAG Test Data Input
8
SS
SS
SS
SS
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
Data Outputs
No Connect
Input Clock
Data Inputs
Ground
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
S A
S A
DDQ
9
TM
V
II b2 SRAM
SS
V
TMS
NC
NC
NC
NC
NC
NC
Q 7
D6
Q 4
D3
Q 1
D0
10
REF
/SA*
Dec. 2003
Rev 2.0
TDI
NOTE
C Q
Z Q
Q 8
D8
D7
Q 6
Q 5
D5
D4
Q 3
Q 2
D2
D1
Q 0
11
1
2
3