k7r321882m Samsung Semiconductor, Inc., k7r321882m Datasheet - Page 8
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k7r321882m
Manufacturer Part Number
k7r321882m
Description
1mx36-bit, 2mx18-bit, 4mx9-bit Qdrtm Ii B2 Sram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K7R321882M.pdf
(19 pages)
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K7R323682M
K7R321882M
K7R320982M
Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ " refers to read inactive status with R=high. "WRITE" and " WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.
READ
ALWAYS
(FIXED)
READ ADDRESS
LOAD NEW
READ NOP
DDR READ
READ
1Mx36 & 2Mx18 & 4Mx9 QDR
STATE DIAGRAM
READ
READ
POWER-UP
- 8 -
WRITE
WRITE
WRITE PORT NOP
WRITE ADDRESS
WRITE
WRITE NOP
DDR WRITE
LOAD NEW
ALWAYS
(FIXED)
TM
II b2 SRAM
WRITE
Dec. 2003
Rev 2.0