w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 23

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

3.5.17 Direct-d
With Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to
form the effective address. An additional cycle is required when the Direct Register is not page
aligned (DL not equal 0). The Bank register is always 0.
3.5.18 Immediate-#
With Immediate (#) addressing the operand is the second byte (second and third bytes when in the
16-bit mode) of the instruction.
3.5.19 Implied-i
Implied (i) addressing uses a single byte instruction. The operand is implicitly defined by the instruction.
3.5.20 Program Counter Relative Long-rl
The Program Counter Relative Long (rl) addressing mode is used with only with the unconditional
Branch Long instruction (BRL) and the Push Effective Relative instruction (PER). The second and
third bytes of the instruction are added to the Program Counter, which has been updated to point to
the opcode of the next instruction. With the branch instruction, the Program Counter is loaded with
the result. With the Push Effective Relative instruction, the result is stored on the stack. The offset is
a signed 16-bit quantity in the range from -32768 to 32767. The Program Bank Register is not
affected.
3.5.21 Program Counter Relative-r
The Program Counter Relative (r) addressing is referred to as Relative Addressing and is used only
with the Branch instructions. If the condition being tested is met, the second byte of the instruction is
added to the Program Counter, which has been updated to point to the opcode of the next instruction.
The offset is a signed 8-bit quantity in the range from -128 to 127. The Program Bank Register is not
affected.
3.5.22 Stack-s
Stack (s) addressing refers to all instructions that push or pull data from the stack, such as Push, Pull,
Jump to Subroutine, Return from Subroutine, Interrupts, and Return from Interrupt. The bank address
is always 0. Interrupt Vectors are always fetched from Bank 0.
Instruction:
Operand
Address:
Opcode
00
+
offset
effective address
Direct Register
offset
23