A43E06321G-75F AMICC [AMIC Technology], A43E06321G-75F Datasheet - Page 20

• Manufacturer Part Number: A43E06321G-75F
• Description: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
PRELIMINARY
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
Internal
Internal
1) Clock Suspend (=Active Power Down) Exit
1) Auto Refresh
2) Self Refresh
CLK
CLK
No precharge commands are required after Auto Refresh command.
During t
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During t
Before/After self refresh mode,
REFRESH and AUTO REFRESH utilize the row refresh counter.
CKE
CKE
CMD
CMD
CLK
CLK
CMD
CLK
CKE
(July, 2005, Version 0.0)
Note 1
RC
RC
from auto refresh command, any other command can not be accepted.
from self refresh exit command, any other command can not be accepted.
PRE
PRE
Note 3
Note 6
Note 4
Note 4
t
t
RP
RP
SR
AR
AUTO REFRESH commands must be issued every 15.6 μ s or less as both SELF
t
SS
RD
19
t
RC
2) Power Down (=Precharge Power Down) Exit
Internal
CLK
CKE
CMD
CLK
t
RC
CMD
Note 2
Note 5
AMIC Technology, Corp.
CMD
NOP
t
SS
ACT
A43E06321