A43E06321G-75F AMICC [AMIC Technology], A43E06321G-75F Datasheet - Page 38

• Manufacturer Part Number: A43E06321G-75F
• Description: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

CLOCK
A10/AP
ADDR
Self Refresh Entry & Exit Cycle
PRELIMINARY
RAS
CAS
CKE
DQM
CS
DQ
WE
BA
0
* Note 7
* Note : TO ENTER SELF REFRESH MODE
Self Refresh Entry
t
1
SS
* Note 1
TO EXIT SELF REFRESH MODE
1.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
4. System clock restart and be stable before returning CKE high.
5.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. Before/After self refresh mode, AUTO REFRESH commands must be issued every 15.6μs or less as both SELF
(July, 2005, Version 0.0)
2
CS , RAS & CAS with CKE should be low at the same clock cycle.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
CS starts from high.
REFRESH and AUTO REFRESH utilize the row refresh counter.
* Note 2
Hi-Z
3
4
5
6
* Note 3
7
8
9
37
Hi-Z
10
* Note 4
Self Refresh Exit
11
* Note 5
t
12
SS
13
t
RC min.
14
AMIC Technology, Corp.
* Note 6
15
Auto Refresh
* Note 7
16
A43E06321
17
18
: Don't care
19