A43L2616AG-6 AMICC [AMIC Technology], A43L2616AG-6 Datasheet - Page 14

• Manufacturer Part Number: A43L2616AG-6
• Description: 1M X 16 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy t
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A10/AP. If burst read or burst
write command is issued with low on A10/AP, the bank is
left active until a new command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
Four Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on
t
At the end of tRP after performing precharge all, both
banks are in idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal
counter increments automatically on every auto refresh
cycle to refresh all the rows. An auto refresh command is
issued by asserting low on
on CKE and
asserted with both banks being in idle state and the device
is not in power down mode (CKE is high in the previous
cycle). The time required to complete the auto refresh
PRELIMINARY
WE
RAS
(min) requirement, performs precharge on both banks.
with high on A10/AP after both banks have satisfied
WE
. The auto refresh command can only be
(November, 2004, Version 0.0)
RAS
(min) and “t
CS
,
RAS
RP
” for the programmed
and
CS
CAS
,
RAS
with high
and
13
operation is specified by “t
of clock cycles required can be calculated by driving “t
with clock cycle time and then rounding up to the next
higher integer. The auto refresh command must be
followed by NOP’s until the auto refresh operation is
completed. Both banks will be in the idle state at the end of
auto refresh operation. The auto refresh is the preferred
refresh mode when the SDRAM is being used for normal
data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once
in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
The self refresh mode is entered from all banks idle state
by asserting low on
on WE . Once the self refresh mode is entered, only CKE
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “t
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 4096 auto refresh cycles
immediately after exiting self refresh.
CS
AMIC Technology, Corp.
,
RAS
RC
(min)”. The minimum number
,
CAS
RC
” before the SDRAM
and CKE with high
A43L2616A
RC
”