A43L2616AG-6 AMICC [AMIC Technology], A43L2616AG-6 Datasheet - Page 9

• Manufacturer Part Number: A43L2616AG-6
• Description: 1M X 16 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Simplified Truth Table
Register
Refresh
Bank Active & Row Addr.
Read &
Column Addr. Auto Precharge Enable
Write &
Column Addr. Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
Note : 1. OP Code: Operand Code
PRELIMINARY
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions as same as CBR refresh of DRAM.
4. BS0, BS1 : Bank select address.
5. During burst read or write with auto precharge, new read write command cannot be issued.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but
A0~A11, BS0, BS1: Program keys. (@MRS)
A new command can be issued after 2 clock cycle of MRS.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.
Another bank read write command can be issued at every burst length.
masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Disable
Bank Selection
Both Banks
Command
(November, 2004, Version 0.0)
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
X
H
H
X
X
X
X
X
H
H
X
L
L
L
CS
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
8
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
RAS CAS
H
H
X
H
H
H
X
X
H
X
V
X
H
X
L
L
L
L
X
H
H
H
H
H
H
H
X
X
X
X
V
X
X
L
L
L
L
WE
H
H
H
H
H
H
H
X
L
X
X
X
V
X
X
L
L
L
DQM BS0
AMIC Technology, Corp.
X
X
X
X
X
X
X
X
X
X
X
X
X
V
BS1
V
V
V
V
X
OP CODE
A10
/AP
H
H
H
L
L
L
Row Addr.
X
X
X
X
X
X
X
A43L2616A
Column
Column
A9~A0,
Addr.
Addr.
A11
X
Notes
1,2
4,5
4,5
3
3
3
3
4
4
4
6