A43L2616AG-6 AMICC [AMIC Technology], A43L2616AG-6 Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
A43L2616AG-6
Manufacturer Part Number
A43L2616AG-6
Description
1M X 16 Bit X 4 Banks Synchronous DRAM
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A43L2616AG-6.pdf
(42 pages)
- Current page: 8 of 42
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Operating AC Parameter
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
PRELIMINARY
Symbol
t
t
t
t
t
t
t
t
RAS(max)
RRD(min)
RCD(min)
t
t
CCD(min)
RAS(min)
CDL(min)
RDL(min)
BDL(min)
RP(min)
RC(min)
2. Minimum delay is required to complete write.
then rounding off to the next higher integer.
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in new col. Address delay
Last data in row precharge
Last data in to burst stop
Col. Address to col. Address delay
RAS to
(November, 2004, Version 0.0)
CAS
Parameter
delay
CAS Latency
7
3
12
18
18
42
60
12
-6
6
6
6
Version
100
AMIC Technology, Corp.
14
20
20
42
63
14
-7
7
7
7
A43L2616A
Unit
µ s
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
1
1
1
2
2
2
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