S1D13305D00A EPSON [Epson Company], S1D13305D00A Datasheet - Page 51

• Manufacturer Part Number: S1D13305D00A
• Description: LCD Controller ICs
• Manufacturer: EPSON [Epson Company]

9.2.3. Display scan timing
Figure 32 shows the basic timing of the S1D13305 series.
One display memory read cycle takes nine periods of the
system clock, 0 (
times per display line.
When reading, the display memory pauses at the end of
each line for (TC/R - C/R) display memory read cycles,
S1D13305 Series
Technical Manual
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
VCE
VA
0
only at the end of the lower screen’s display interval.
Frame
period
f
OSC
Character read interval
). This cycle repeats (C/R + 1)
T0
Figure 33. Relationship between TC/R and C/R
Figure 32. Display memory basic read cycle
Line 1
(L/F)
LP
2
3
Display read cycle interval
Graphics read interval
EPSON
T1
Display period
though the LCD drive signals are still generated. TC/R
may be set to any value within the constraints imposed by
C/R,
be used to fine tune the frame frequency. The micropro-
cessor may also use this pause to access the display
memory data.
TC/R
C/R
O
O
O
•
•
•
•
•
O
f
OSC
,
Character generator
f
FR
DISPLAY CONTROL FUNCTIONS
read interval
, and the size of the LCD panel, and it may
T2
Divider frequency
period
R
R
R
R
45