S1D13305D00A EPSON [Epson Company], S1D13305D00A Datasheet - Page 69

• Manufacturer Part Number: S1D13305D00A
• Description: LCD Controller ICs
• Manufacturer: EPSON [Epson Company]

12.2. Supply Current during Display Memory Access
The 24 address and data lines of the S1D13305 series
cycle at one-third of the oscillator frequency, f
charge and discharge current on these pins, I
by the equation below. When I
estimated by:
where C is the capacitance of the display memory bus, V
is the operating voltage, and f is the operating frequency.
13. OSCILLATOR CIRCUIT
The S1D13305 series incorporates an oscillator circuit. A
stable oscillator can be constructed simply by connecting
an AT-cut crystal and two capacitors to XG and XD, as
shown in the figure below. If the oscillator frequency is
increased, C
ally.
Note that the circuit board lines to XG and XD must be as
short as possible to prevent wiring capacitance from
changing the oscillator frequency or increasing the power
consumption.
14. STATUS FLAG
The S1D13305 series has a single bit status flag.
D6: X line standby
S1D13305 Series
Technical Manual
CS
I
0
VOP
D7
X D6
XSCL
LP
C V f
D
A0
0
X
and C
Figure 53. Status flag
X
G
RD
X
should be decreased proportion-
0
DISPLAY MEMORY INTERFACE/OSCILLATOR CIRCUIT/STATUS FLAG
X
VOP
0: Period of retrace lines
1: Period of display
X
exceeds I
D0
X
Figure 54. C/R to TC/R time difference
D
X: Don’t care
6
(flag)
t
OPR
m
VOP
, it can be
OSC
, is given
. The
EPSON
If V
capacitance is 1.0 pF per line:
To reduce current flow during display memory accesses,
it is important to use low-power memory, and to mini-
mize both the number of devices and the parasitic capaci-
tance.
The D6 status flag is HIGH for the TC/R-C/R cycles at the
end of each line where the S1D13305 series is not reading
the display memory. The microprocessor may use this
period to update display memory without affecting the
display, however it is recommended that the display be
turned off when refreshing the whole display.
t
TC/R
OPR
I
VOP
S1D13305 series
= 5.0V, f = 1.0 MHz, and the display memory bus
120 A / MHz pF
XG
t
Figure 52. Crystal oscillator
C/R
C
G
XD
C
D
C
C
Load impedance = 700
D
G
= 3 to 20 pF
= 2 to 18 pF
(max)
63