A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 13

• Manufacturer Part Number: A40MX02-PL208A
• Description: 40MX and 42MX Automotive FPGA Families
• Manufacturer: ACTEL [Actel Corporation]

Table 1-3 • Test Access Port Descriptions
Table 1-4 • Supported BST Public Instructions
Port
TMS
Select)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge
TDI (Test Data Input)
TDO
Output)
Instruction
EXTEST
SAMPLE/PRELOAD
HIGH Z
CLAMP
BYPASS
(Test
(Test
Mode
Data
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK)
of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency
for TCK is 20 MHz
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high
impedance) when data scanning is not in progress
IR Code [2:0]
000
001
101
110
111
Instruction Type
Mandatory
Mandatory
Mandatory
Optional
Optional
v3.1
Allows the external circuitry and board-level interconnections to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins
Allows a snapshot of the signals at the device pins to be
captured and examined during operation
Tristates all I/Os to allow external signals to drive pins. Please
refer to the IEEE Standard 1149.1 specification for details
Allows state of signals driven from component pins to be
determined from the Boundary-Scan Register. Please refer to
the IEEE Standard 1149.1 specification for details
Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices
in the test chain
Description
40MX and 42MX Automotive FPGA Families
Description
1-9