A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 20
![no-image](/images/no-image-200.jpg)
A40MX02-PL208A
Manufacturer Part Number
A40MX02-PL208A
Description
40MX and 42MX Automotive FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A40MX02-PL208A.pdf
(78 pages)
- Current page: 20 of 78
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Timing Information
Note: * Values are shown for 40MX at worst-case 5.0V automotive conditions.
Figure 1-15 • 40MX Timing Model*
Notes:
Figure 1-16 • 42MX Timing Model*
1 -1 6
40MX and 42MX Automotive FPGA Families
Clock
Clocks
Array
*Values are shown for A42MX09 at worst-case 5.0V automotive conditions.
† Input module predicted routing delay
Array
I/O Module
F
I/O Module
MAX
t
t
F
t
INGL
INSU
MAX
INH
t
CKH
t
= 192 MHz
= 0.0 ns
= 0.4 ns
= 2.1 ns
Input Delay
CKH
Input Delays
= 116 MHz
D
G
= 4.0 ns
t
t
= 8.1 ns
INYL
INYL
Q
= 1.2 ns
= 1.3 ns
FO = 32
FO = 128
t
t
t
t
IRD4
IRD8
IRD2
IRD1
3.4 ns
t
IRD1
= 6.5 ns
= 10.2 ns
= 4.6 ns
= 3.7 ns
=
†
t
t
SUD
t
LCO
HD
Combin-
included
atorial
Logic
in t
Combinatorial
Internal Delays
Logic Module
= 0.4 ns
= 0.0 ns
= 8.6 ns (light loads, pad-to-pad)
Internal Delays
t
SUD
Logic Module
PD
t
t
Logic Module
PD
CO
= 2.0 ns
Sequential
= 2.2 ns
= 2.2 ns
v3.1
t
CO
D
= 2.1 ns
t
t
t
t
t
t
t
t
RD1
RD2
RD4
RD8
RD2
RD4
RD8
RD1
Q
Predicted
Predicted
Routing
Routing
Delays
Delays
= 5.1 ns
= 8.8 ns
= 2.3 ns
= 3.2 ns
= 1.1 ns
= 1.6 ns
= 2.2 ns
= 3.8 ns
t
RD1
= 1.1 ns
I/O Module
I/O Module
I/O Module
t
t
OUTSU
t
Output Delay
OUTH
ENHZ
t
D
Output Delays
G
GLH
t
DLH
t
DLH
= 0.00 ns
= 0.4 ns
= 4.3 ns
= 14.1 ns
Q
t
= 5.9 ns
DLH
= 4.0 ns
= 4.0 ns
t
ENHZ
= 8.2 ns
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