SST25VF010-20-4C-QA-DD029 SST [Silicon Storage Technology, Inc], SST25VF010-20-4C-QA-DD029 Datasheet - Page 8

• Manufacturer Part Number: SST25VF010-20-4C-QA-DD029
• Description: 1 Mbit SPI Serial Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
Read
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
©2003 Silicon Storage Technology, Inc.
FIGURE 4: R
FIGURE 5: B
SCK
CE#
SO
SI
MODE 3
MODE 0
EAD
YTE
MSB
-P
0 1 2 3 4 5 6 7 8
S
ROGRAM
EQUENCE
SCK
CE#
SO
SI
03
MODE 3
MODE 0
HIGH IMPEDANCE
S
EQUENCE
MSB
0 1 2 3 4 5 6 7 8
MSB
ADD.
02
15 16
ADD.
HIGH IMPEDANCE
23 24
MSB
8
ADD.
ADD.
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait T
self-timed Byte-Program operation. See Figure 5 for the
Byte-Program sequence.
MSB
31 32
15 16
D
ADD.
OUT
N
39 40
23 24
D
N+1
ADD.
OUT
47 48
31 32
MSB
D
N+2
OUT
D
BP
1233 F05.1
1 Mbit SPI Serial Flash
IN
LSB
for the completion of the internal
55 56
39
D
N+3
OUT
63 64
23
D
SST25VF010
N+4
1233 F04.1
S71233-01-000
OUT
-A
23
0
-A
]. Following the
70
0
]. CE# must
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