ls7266r1 LSI Computer Systems, Inc., ls7266r1 Datasheet - Page 8

• Manufacturer Part Number: ls7266r1
• Description: 24-bit Dual-axis Quadrature Counter
• Manufacturer: LSI Computer Systems, Inc.

7266R1-100704-8
Y-AXIS I/Os:
All the X-axis inputs/outputs are duplicated for the Y-axis with similar functionalities.
COMMON I/Os:
X-AXIS I/Os:
XA (Pin 20)
XB (Pin 21)
XLCNTR/XLOL
(Pin 19)
XRCNTR/XABG
(Pin 18)
XFLG1 (Pin 22)
XFLG2 (Pin 23)
YA (Pin 25)
YB (Pin 24)
YLCNTR/YLOL (Pin 1)
YRCNTR/YABG (Pin 28)
YFLG1 (Pin 27)
YFLG2 (Pin 26)
WR (Pin 14)
RD (Pin 16)
CS (Pin 15)
C/D (Pin 13)
D0 - D7
(Pins 4 - 11)
FCK (Pin 2)
X/Y (Pin 17)
V
V
DD
SS
(Pin 12)
(Pin 3)
X-axis count input A
X-axis count input B
X-axis programmable input, to operate as either direct load XCNTR or direct load XOL or synchronous
load XCNTR or synchronous load XOL. The synchronous load mode is intended for interfacing with
the encoder Index output in quadrature clock mode. In direct load mode, a logic low level is the active
level at this input. In synchronous load mode the active level can be programmed to be either logic
low or logic high. Both quarter-cycle and half-cycle Index signals are supported by this input in the in-
dexed Load mode. The synchronous function must be disabled in non-quadrature count mode (See
description of IDR on P. 4)
X-axis programmable input to operate either as direct reset XCNTR or count enable/disable gate or
synchronous reset XCNTR. The synchronous reset XCNTR mode is intended for interfacing with the
encoder Index output in quadrature clock mode. In direct reset XCNTR mode, a logic low level is the
active level at this input whereas in synchronous reset XCNTR mode the active level can be pro-
grammed to be either a logic low or a logic high. Both quarter-cycle and half-cycle index signals are
supported by this input in the indexed reset CNTR mode. The synchronous function must be disabled
in non-quadrature count mode (See description of IDR on P. 4). In count enable/disable mode, a logic
high at this input enables the counter and a logic low level disables the counter.
X-axis programmable output to operate either as XCARRY (Active low), or XCOMPARE (generated
when XPR=XCNTR; Active low), or XIDX (XFLAG bit 6) or XCARRY/XBORROW (Active low).
X-axis programmable output to operate as either XBORROW (Active low) or XU/D (XFLAG bit 5)
or XE (XFLAG bit 4).
Write input. Control/data bytes are written at the trailing edge of low level pulse applied to this input.
Read input. A low level applied to this input enables the FLAGs and OLs to be read on the data bus.
Chip select input. A low level applied to this input enables the chip for Read and Write.
Control/Data input. This input selects between a control register or a data register for Read/Write.
When low, a data register is selected. When high, a control register is selected.
Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers
take place between the LS7266R1 and the host processor.
Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable
prescalers, one for each channel.
Selects between X and Y axes for Read or Write. X/Y = 0 selects X-axis and X/Y = 1 selects Y-axis.
X/Y is overridden by D7 = 1 in Control Write Mode (C/D = 1).
+5V
GND
Either quadrature encoded clocks or non-quadrature clocks can be applied
to XA and XB. In quadrature mode XA and XB are digitally filtered and decoded
for UP/DN clock. In non-quadrature mode, the filter and the decoder circuits are
by-passed. Also, in non-quadrature mode XA serves as the count input and XB
as the UP/DOWN direction control input, with XB = 1 selecting Up Count mode
and XB = 0, selecting Down Count mode.
INPUTS/OUTPUTS