km62256c Samsung Semiconductor, Inc., km62256c Datasheet - Page 2

• Manufacturer Part Number: km62256c
• Description: 32kx8 Bit Low Power Cmos Static Ram
• Manufacturer: Samsung Semiconductor, Inc.

FEATURES
PRODUCT FAMILY
PIN DESCRIPTION
KM62256C Family
32Kx8 bit Low Power CMOS Static RAM
VSS
I/O1
I/O2
I/O3
A14
A12
KM62256CL
KM62256CL-L
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
A7
A6
A5
A4
A3
A2
A1
A0
Process Technology : 0.7 m CMOS
Organization : 32Kx8
Power Supply Voltage : Single 5V 10%
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 28-DIP-600, 28-SOP-450,
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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Product Family
NameName
28-SOP
28-DIP
I/O
A
0
WE
Vcc
CS
OE
1
Vss
~A
~I/O
14
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-TSOP1 -0813.4F/R
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VCC
VCC
A11
A13
A14
A12
A12
A14
A13
A11
WE
WE
OE
OE
A9
A8
A7
A6
A5
A4
A3
A3
A4
A5
A6
A7
A8
A9
Operating Temperature.
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power(5V)
Ground
Commercial (0~70 C)
Extended (-25~85 C)
Industrial (-40~85 C)
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2
3
4
5
6
7
8
9
10
11
12
13
14
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Type I - Forward
Type I - Reverse
28-TSOP
28-TSOP
Function
28
27
26
25
24
23
22
21
20
19
18
17
16
15
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Speed(ns)
55/70ns
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
70ns
70ns
2
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
CMOS process technology. The family supports various operat-
ing temperature ranges and has various package types for user
flexibility of system design. The family also support low data
retention voltage for battery back-up operation with low data
retention current.
The KM62256C family is fabricated by SAMSUNG s advanced
CS
WE
OE
28-DIP, 28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
I/O
I/O
1
8
PKG Type
Control
Logic
A3
A4
A5
A6
A7
A8
A12
A13
A14
Clk gen.
Data
cont
Data
cont
Row
select
(I
Standby
SB1
100 A
100 A
100 A
20 A
50 A
50 A
Power Dissipation
A0
, Max)
CMOS SRAM
A1
Precharge circuit.
Memory array
512 rows
64 8 columns
Column select
A2
I/O Circuit
December 1997
A9
Operating
Revision 4.0
A10
70mA
(Icc
A11
2
)