AD671KD-500 AD [Analog Devices], AD671KD-500 Datasheet - Page 10

• Manufacturer Part Number: AD671KD-500
• Description: Monolithic 12-Bit 2 MHz A/D Converter
• Manufacturer: AD [Analog Devices]

AD671
it should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately 50 mV of offset trim range.
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (9.9963 for a 10 V range). Trim R1 to give
the last transition (1111 1111 1110 to 11111111 1111).
UNIPOLAR (0 V TO +5 V) CALIBRATION
The connections for the 0 V to +5 V input range calibration is
shown in Figure 8. The AD586, a +5 V precision voltage refer-
ence, is an excellent choice for this mode of operation because
of its performance, stability and optional fine trim. The AD845
(16 MHz, low power, low cost op amp) is used to maintain the
+5 volts under the dynamically changing load conditions of the
reference input.
The AD671 offset error must be trimmed within the analog in-
put path, either directly in front of the AD671 or within the sig-
nal conditioning chain, eliminating offset errors induced by the
signal conditioning circuitry. Figure 8 shows an example of how
the offset error can be trimmed in front of the AD671. The
AD586 is configured in the optional fine trim mode to provide
+6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure
for trimming the offset and gain errors is similar to that used for
the unipolar 10 V range with the analog input values set to one-
half the 10 V range values.
BIPOLAR ( 5 V) CALIBRATION
The connections for the bipolar input range is shown in Figure
9. The AD588 is configured to provide dual +5 V outputs. Pro-
viding a +5 V reference voltage for the AD671 gain trim and the
+5 V BPO/UPO input for the bipolar offset trim.
1 F
1 F
Figure 8. Unipolar (0 V to +5 V) Calibration
5
8
7
+ 15V
NOISE
REDUCTION
+V
9
Figure 9. Bipolar ( 5 V) Calibration
2
AD586
IN
10
4
AD588
6
0 TO +5V
GND
TRIM
V
8
+
OUT
15V
4
12
39k
6
5
–15V
11
3
2
3
0.1 F
6.2k
+15V
150pF
13
10k
AD845
4
2
3
14
15
16
1
2
AD845 6
1
7
–15V
1k
7
100
+ 15
–15
4
R1
150pF
8
+15V
50
50
0.1 F
6
0.1 F
0.1 F
10 F
10 F
390
100
R2
5V
+15V
0.1 F
0.1 F
20
22
18
19
21
V
AIN
BPO/UPO
ACOM
DCOM
REFIN
18
19
23
20
22
21
CC
23
V
AIN
ACOM
DCOM
REF IN
BPO/UPO
CC
AD671
V
24
EE
AD671
V
EE
ENCODE
24
V
17
LOGIC
ENCODE
BIT12
MSB
DAV
BIT1
OTR
BIT12
MSB
V
DAV
BIT1
OTR
LOGIC
17
12
16
15
14
13
1
12
16
15
14
13
1
–10–
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963) is applied, and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
OUTPUT LATCHES
Figure 10 shows the AD671 connected to the 74HC574 Octal
D-type edge triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum set-up and
hold times of the 574 type latch must be less than 20 ns (t
and t
latch the recommended logic families are HC, S, AS, ALS, F or
BCT. New data from the AD671 is latched on the rising edge of
the DAV (Pin 24) output pulse. Previous data can be latched by
inverting the DAV output with a 7404 type inverter. See Fig-
ures 20, 21 and 22 for PCB layout recommendations.
OUT OF RANGE
An Out of Range condition exists when the analog input voltage
is beyond the input range (0 V to +5 V, 0 V to +10 V, 5 V) of
the converter. OTR (Pin 14) is set low when the analog input
voltage is within the analog input range. OTR is set HIGH and
will remain HIGH when the analog input voltage exceeds the
input range by typically 1/2 LSB (OTR transition is tested to
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 11. Sys-
tems requiring programmable gain conditioning prior to the
AD671 can immediately detect an out of range condition, thus
eliminating gain selection iterations.
6 LSBs of accuracy) from the center of the
SS
minimum). To satisfy the requirements of the 574 type
OTR
0
0
1
1
AD671
Figure 10. AD671 to Output Latches
Table II. Out of Range Truth Table
BIT10
BIT12
BIT11
BIT5
BIT6
BIT9
BIT2
BIT3
BIT4
BIT7
BIT8
BIT1
DAV
MSB
0
1
0
1
1D
1D
2D
3D
4D
5D
6D
7D
8D
2D
3D
4D
5D
7D
8D
CLK
CLK
6D
74HC574
74HC574
U6
U5
Analog Input Is
In Range
In Range
Underrange
Overrange
OC
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
1Q
5Q
6Q
7Q
8Q
8Q
2Q
3Q
4Q
DATA BUS
full-scale output
3-STATE
CONTROL
REV. B
DD