lc75857e Sanyo Semiconductor Corporation, lc75857e Datasheet
lc75857e
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lc75857e Summary of contents
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... LC75857W Overview The LC75857E and LC75857W are 1/3 duty and 1/4 duty LCD display drivers that can directly drive up to 164 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from keys to reduce printed circuit board wiring. ...
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... CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time DO output delay time DO rise time Note: *1. Since open-drain output, these values depend on the resistance of the pull-up resistor R LC75857E, LC75857W =0V SS Symbol Conditions V max V DD ...
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... Output middle level voltage * Oscillator frequency Current drain Nete: *2. Excluding the bias voltage generation divider resistor built into V Package Dimensions unit: mm 3159A-QIP64E [LC75857E] 17.2 14 0.8 0.35 (1.0) LC75857E, LC75857W Symbol Conditions V CE, CL KI1 to KI5 H2 V DET I 1 CE, CL OSC ...
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... Serial data I/O timing when CL is stopped at the high level CE t ø ø tds DO 3. OSC pin clock timing in external clock mode t CK VIH3 50% OSC VIL3 LC75857E, LC75857W V LCD 1 To the common segment driver 2 Excluding these registors. Figure 1 VIH1 t ø tcp tcs D0 Figure 2 VIH1 ...
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... Pin Assignments 48 49 KI1 KI2 KI3 KI4 KI5 VDD VLCD VLCD1 VLCD2 VSS TEST OSC LC75857E, LC75857W LC75857E S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 17 16 Top view ...
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... Block Diagram VLCD VLCD1 COMMON DRIVER VLCD2 VSS TEST CLOCK OSC GENERATOR DO CCB DI INTERFACE CL CE VDD VDET LC75857E, LC75857W SEGMENT DRIVER & LATCH CONTROL REGISTER SHIFT REGISTER KEY BUFFER KEY SCAN No. 7980-6/39 ...
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... LCD driver block power supply connection. A voltage in the range 0.75 must be provided when VDD is in the range 3.6 to 6.0 V, and a voltage in the range V 55 LCD 2 6.0 V must be provided when VDD is in the range 2 Power supply connection. Connect to ground. SS LC75857E, LC75857W Function VDD to 6.0 V Handling Active I/O when unused — O OPEN — ...
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... Display data D85 D86 Display data Note B3 ...... CCB address DD ................................ Direction data LC75857E, LC75857W D41 D42 KC0 KC1 KC2 KSC K0 K1 Control data D83 D84 ...
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... .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data LC75857E, LC75857W D41 D42 ...
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... Display data D125 Display data Note B3 ...... CCB address DD ................................ Direction data LC75857E, LC75857W D40 D41 D42 D43 D44 0 SP KC0 KC1 KC2 KSC Display data D84 ...
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... .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data LC75857E, LC75857W D40 D41 D42 D43 D44 0 ...
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... S40 S41 1 1 S40 S41 Note: KSn Key scan output 42): Segment output LC75857E, LC75857W Common and segment External clock mode pin output states External clock signal accepted LCD drive waveforms Acceptance of the external clock signal is disabled. during key scan operations) ...
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... DT : 1/3 duty or 1/4 duty drive selection data This control data bit switches between LCD 1/3 duty or 1/4 duty drive. DT Duty drive scheme 0 1/4 duty drive 1 1/3 duty drive Note: COM4: Common output S39 : Segment output LC75857E, LC75857W Output pin state S2/P2 S3/P3 S4/ ...
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... The LCD segment for COM1 is on The LCD segments for COM1 and COM3 are on The LCD segments for COM1 and COM2 are on The LCD segments for COM1, COM2 and COM3 are on. LC75857E, LC75857W /768 CK /576 CK /384 CK /288 CK /192 CK Output pin COM1 ...
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... The LCD segments for COM1,COM2 and COM4 are on The LCD segments for COM1,COM2 and COM3 are on The LCD segments for COM1,COM2,COM3 and COM4 are on. LC75857E, LC75857W COM4 Output pin COM1 D4 S22 D85 D8 S23 D89 D12 S24 D93 ...
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... Note B3 A3······CCB address CCB address ...... 43H KD1 to KD30 ........ Key data SA ........................ Sleep acknowledge data Note key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid. LC75857E, LC75857W ...
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... Thus this mode reduces power consumption. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under control of the bits in the control data even in sleep mode. Sleep mode is cancelled by setting SP in the control data to 0. LC75857E, LC75857W KI3 KI4 ...
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... However high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performes another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between kΩ ...
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... However high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ ...
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... DO Multiple Key Presses Although the LC75857E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key ...
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... When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data LC75857E, LC75857W fo[Hz] 1/3 Duty, 1/2 Bias Waveforms f ...
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... When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data LC75857E, LC75857W fo[Hz] 1/3 Duty, 1/3 Bias Waveforms f ...
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... When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data LC75857E, LC75857W fo[Hz] 1/4 Duty, 1/2 Bias Waveforms f ...
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... When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data LC75857E, LC75857W fo[Hz] 1/4 Duty, 1/3 Bias Waveforms f ...
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... System Reset The LC75857E/W supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. ...
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... VDD VLCD D44, SP, KC0 to KC2, KSC, K0, Internal data K1 P2, SC, DR, DT,FC0 to FC2, OC Internal data (D45 to D84) Internal data (D85 to D124) Internal data (D125 to D164) LC75857E, LC75857W t1 t2 VDET VIL1 Display and control data transfer Undefined Defined Undefined Defined Undefined System reset period Note: t1 ≥ ...
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... LC75857E/W internal block states during the reset period • CLOCK GENERATOR A reset is applied and either the OSC pin oscillator is stopped or external clock input is stopped. • COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. ...
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... OSC pin and the external clock output pin (external oscillator). The value of this resistor is determined by the allowable current for the external clock output pin. Verify that the external clock waveform is not deformed significantly. Note: The external clock output pin allowable current must be greater than VDD/Rg. LC75857E, LC75857W OSC Rosc Cosc ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage V block power supply voltage V fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. DD *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4 kΩ ...
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... Notes on transferring display data from the controller When using the LC75857E/W in 1/3 duty, applications transfer the display data (D1 to D126) in three operations, and in 1/4 duty, they transfer the display data (D1 to D164) in four operations. In either case, applications should transfer all of the display data within maintain the quality of the displayed image ...
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... The period t9 in this technique must satisfy the following condition. t9>t6+t7+ key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. LC75857E, LC75857W ...
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... Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time t8: Key data read time LC75857E, LC75857W NO Key on t5 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2004. Specifications and information herein are subject to change without notice. LC75857E, LC75857W PS No. 7980-39/39 ...