lc75712e Sanyo Semiconductor Corporation, lc75712e Datasheet - Page 11

• Manufacturer Part Number: lc75712e
• Description: Dot Matrix Vfd Display Controller/driver
• Manufacturer: Sanyo Semiconductor Corporation

3. Display shift .........................................<Shifts the display.>
4. Grid register load .................................<Specifies the number of digits displayed.>
G1 to G16: Display digit specification
Each bit Gn (where n is an integer between 1 and 16) specifies that the corresponding grid output pin Gn be turned
on when that bit (Gn) is 1.
This instruction is used to specify the display on/off control operation. Not only can an arbitrary digit be specified,
but MDATA and ADATA can also be specified.
*: Don’t care.
M, A: Specifies the data to be shifted.
R/L: Shift direction specification
*: Don’t care.
GN0 to GN3: Displayed digits specification
The AA4/G16, AA5/G15, AA6/G14, AA7/G13, and AA8/G12 anode/grid output pins function as grid output pins if
between 12 and 16 digits are selected. Also, this instruction must be executed prior to turn the display on since the
value of the grid register is undefined immediately after power is applied.
GN3 GN2 GN1 GN0 HEX
D23 D22 D21 D20 D19
D23 D22 D21 D20 D19
R/L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
M
0
0
0
1
1
0
1
0
Right shift
Left shift
0
A
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Neither MDATA nor ADATA are shifted.
Only ADATA is shifted.
Only MDATA is shifted.
Both MDATA and ADATA are shifted.
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GN3 GN2 GN1 GN0
C
D
*
0
1
2
3
4
5
6
7
8
9
A
B
E
F
Shift operating state
Shift direction
G1 to G16
G1
G1 to G2
G1 to G3
G1 to G4
G1 to G5
G1 to G6
G1 to G7
G1 to G8
G1 to G9
G1 to G10
G1 to G11
G1 to G12
G1 to G13
G1 to G14
G1 to G15
D18 D17 D16
D18 D17 D16
M
A
Digits Controlled
R/L
LC75710NE, 75711NE, 75712E
D15
D15
*
*
D14 D13 D12 D11 D10
D14 D13 D12 D11 D10
*
*
*
*
*
*
Code
Code
*
*
*
*
D9
D9
*
*
D8
D8
*
*
D7
D7
*
*
D6
D6
*
*
D5
D5
*
*
D4
D4
*
*
D3
D3
*
*
D2
D2
No. 4907-11/21
*
*
D1
D1
*
*
D0
D0
*
*