w89c926 Winbond Electronics Corp America, w89c926 Datasheet
w89c926
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w89c926 Summary of contents
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... TWISTED PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C926 PENTIC CMOS device designed for easy implementation of PCMCIA R2.1 compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into a single chip all the registers and logic necessary to connect the SLCT to buffer SRAMs, flash memories (or an EEPROM), and the PCMCIA system bus ...
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... W89C926 PENTIC ...
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... IOWR is asserted by the system to write data to the card's I/O space. It has an internal 100K ohm pull-high resistor. I/TTL Write Enable: The WE input is asserted by the system to strobe memory write data into the card memory. It has an internal 100K ohm pull-high resistor W89C926 PENTIC+ DESCRIPTION Publication Release Date: January 1996 Revision A1 ...
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... A RESET pulse will initiate the PENTIC+'s initialization procedure, including auto-ID/configuration loading, register initialization, and state machine initialization. The pulse width should be at least 500 recognized as a valid reset. This pin has an internal 100K ohm pull-up resistor W89C926 PENTIC+ DESCRIPTION HD15-HD8 HD7-HD0 Valid Valid Valid ...
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... EEPROM. O/TTL Memory Support Read: MSRD is asserted by the PENTIC+ to strobe read data from the on-board memory. Both SRAM and flash memory use MSRD as the read command strobe W89C926 PENTIC+ DESCRIPTION Publication Release Date: January 1996 Revision A1 ...
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... This output asserts low for approximately 50 mS whenever the PENTIC+ transmits or receives data without collisions. This output can also be controlled by the power-down state machine; refer to the descriptions of the COR and CFA registers for more details W89C926 PENTIC+ DESCRIPTION precision resistor precision ...
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... Analog Ground Pins: These pins are the ground to the analog circuitry. Digital Power Supply Pins: These pins supply +5V to the PENTIC+'s digital circuitry. Digital Ground Pins: These pins are the ground to the digital circuitry W89C926 PENTIC+ DESCRIPTION Publication Release Date: January 1996 Revision A1 ...
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... BLOCK DIAGRAM ID Registers Config. Registers & Control Flash Buffer EEPROM Memory Memory Control Control Control Local Bus Interrupt Local Bus Control Arbiter PCMCIA Bus Interface Logic and Drivers HA0-16 HD0-15 PCMCIA slot - 8 - W89C926 PENTIC+ W89C902 Core ...
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... Word Count = nH (n should be set as a non zero value, a zero value will cause an unpredicted error). OSC/XTAL 15 MSD0-7 W89C926 MSA0-16 HA0-16 HD0-15 PCMCIA slot HIGH BYTE - CFB ID-1 ID-3 ID-5 Check Sum - 57H CIS - Publication Release Date: January 1996 - 9 - W89C926 PENTIC+ TP/IF LEDs W89C92 optional LOW BYTE Word Count CFA ID-0 ID-2 ID-4 Board Type (05H) - 57H CIS - Revision A1 ...
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... W89C926 PENTIC+ TYPE Flash Flash Flash Flash Flash Flash Flash Flash Board Type (05H) Flash Flash Flash Flash Flash Flash Flash Flash Flash ...
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... To issue a S/W reset, simply issue an I/O read to the Reset Port. The PENTIC+ will assert a 600 nS internal reset pulse to reset the core state machine. If the host tries to access the PENTIC+, WAIT will be asserted low until the reset is completed. W89C926 PENTIC+ TYPE Memory (SRAM) ...
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... This attribute memory is an image from EEPROM actually resident in upper half of the SRAM after power-on auto- loading. 2. Refer to "Attribute Memory Mapping" for detailed locations. 3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine. W89C926 PENTIC+ NE2000 COMPATIBLE ID Registers ID Registers Buffer SRAM ...
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... The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine. Nonvolatile Memory Mapping (flash memory used) SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 1FFFFH W89C926 PENTIC+ NAME MMA Word/-Byte MMB ID Registers LCE Core Registers MEMORY TYPE SHARED MEMORY MODE ...
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... REGISTER FILE The W89C926 PENTIC+ has four register sets: the core register set, the PCMCIA configuration register set, the LAN configuration register set, and the special control register set. The core register set is the same as that in the W89C90 and will not be discussed here. The other three register sets are described below ...
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... These two registers are used for LAN configuration control. CFA (Configuration Register A) This register is used to select the PENTIC+'s operating mode and LED control. Access Address: AMBase + 00FF0H Access Type: Attribute Memory Read/Write W89C926 PENTIC+ DESCRIPTION DESCRIPTION Publication Release Date: January 1996 - 15 - ...
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... When the physical interface is not configured at TPI or the link checking is disabled, the auto media-switching function will be disabled. DESCRIPTION DESCRIPTION PHY0 Attached Medium Type 0 0 TPI (10BASE-T Compatible Squelch Level) 1 Thin Ethernet (10BASE2 Thick Ethernet (10BASE5) TPI (Reduced Squelch Level W89C926 PENTIC+ ...
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... EEPROM Access Register (EEAR) This register is located on page 3 and is used for EEPROM read/write access control inhibited when EECS/FCS is pulled high. Access Address: IOBase + 02H Access Type: I/O Read/Write W89C926 PENTIC+ DESCRIPTION where ... (after H/W reset) Publication Release Date: January 1996 - 17 - Revision A1 ...
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... If EECS/ FCS is pulled high, this indicates that the configurations are stored in a flash memory. Accordingly, after a power-on reset the PENTIC+ will automatically load the LAN configuration registers from flash memory. The Ethernet IDs stored in the flash memory will be mapped into ID registers automatically when they are read. W89C926 PENTIC+ DESCRIPTION - 18 - ...
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... The exact time for EEPROM loading depends on the length of CIS but must not exceed 10 mS. T > < AUTO T > > 150 nS FOZ W89C926 PENTIC+ T > 150 nS T > FOZ flash address Publication Release Date: January 1996 Revision A1 ...
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... The entire sequence should be consecutive or the process will be aborted > < AUTO T > 0.5 S EEOZ T > 100 nS SW even address 16 bit EEload low byte - 20 - W89C926 PENTIC+ T > > SOZ SOZ T > 100 nS SW odd address high byte ...
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... W89C926 PENTIC+ EECS/ FCS pull low Ethernet Buffer ID0 ID1 ID2 ID3 ID4 ID5 Board Type (05H) Checksum - 57H 57H CIS - Publication Release Date: January 1996 ...
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... DMA starts to move data from buffer memory to the transmit FIFO for transmission receive operation, the local DMA moves received data from the receive FIFO to the buffer and asserts IREQ to the system when the buffer ring needs to be serviced. The system must move data W89C926 PENTIC ...
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... TPI again. If, however, the PENTIC+ is not configured at the TPI or link checking is disabled, the auto media- switching function will be disabled. W89C926 PENTIC+ DESCRIPTION Reserved. Should be set this bit is high, the buffer memory may be accessed by the system ...
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... FIFO logic, and DMA logic. The relationship between these blocks is depicted in the following block diagram. PCMCIA DMA Slot Interface Logic Interface Register access Core Idle access Memory access 16-byte FIFO Register File - 24 - W89C926 PENTIC+ Slave read/ write DMA operation Memory operation Transmit Logic SNA TX/RX Logic Receive Logic ...
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... Since a remote DMA is simply a system I/O operation, it sometimes affects the system bus. If the remote DMA is interleaved with other devices, WAIT is asserted to force the system to insert wait states. The PENTIC+ will automatically handle any arbitration necessary. W89C926 PENTIC+ Publication Release Date: January 1996 - 25 - ...
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... The PENTIC+ also contains a serial network adaptor (SNA), which adapts the non-return-to-zero (NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds of interfacing signals are provided in the PENTIC+: an AUI interface for Ethernet and a coaxial W89C926 PENTIC ...
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... A normal SOI signal An inverted SOI signal A missing SOI signal A missing SOI signal is assumed when no transitions have occurred on the receiver for 175 nS after a packet has arrived. In this case, a normal SOI signal is generated and appended to the data. W89C926 PENTIC+ Transmit PLL Logic Osc/ ...
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... Number of Collisions Register (NCR) 06 FIFO (FIFO) 07 Interrupt Status Register (ISR) 08 Current Remote DMA Address 0 (CRDA0) W89C926 PENTIC+ WRITE Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) Transmit Byte Count Register 1 (TBCR1) ...
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... Physical Address Register 5 (PAR 5) Current Page Register (CURR) Multicast Address 1 (MAR 0) Multicast Address 1 (MAR 1) Multicast Address 2 (MAR 2) Multicast Address 3 (MAR 3) Multicast Address 4 (MAR 4) Multicast Address 5 (MAR 5) Multicast Address 6 (MAR 6) Multicast Address 7 (MAR W89C926 PENTIC+ WRITE WRITE Publication Release Date: January 1996 Revision A1 ...
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... Output Voltage Lead Temperature (soldering 10 seconds maximum) ESD Tolerance Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. W89C926 PENTIC+ WRITE Command (CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) ...
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... PARAMETER Differential Output Voltage (TX+/- ) Differential Output Voltage Imbalance (TX+/-) Undershoot Voltage (TX+/-) Differential Squelch Threshold (CD+/-, RX+/-) Differential Input Common Mode Voltage (CD+/-, RX+/-) W89C926 PENTIC+ SYM. CONDITIONS 5.25V Note 1 AVI 5.25V Note 2 AVT DD SYM. CONDITIONS ...
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... TIB V V TIV V TPS V TNS V TPU V TNU V With test load TO T15 T1 Even Address T10 Valid T7 T8 T13 T12 T11 Valid - 32 - W89C926 PENTIC+ MIN. MAX -2. -3.1 3.1 DD 300 585 -585 -300 200 350 -350 -200 2.2 2.8 Odd Address Valid T14 Valid ...
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... T14 RCS held valid after MSWR deasserted. T15 Even byte address invalid to odd byte address valid. (see note) T16 Command recovery time. Note: This timing is invalid for byte access, e.g, attribute memory reading on SRAM image. DESCRIPTION - 33 - W89C926 PENTIC+ MIN. MAX. UNIT ...
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... T10 Write pulse width T11 FCS asserted to MSWR deasserted T12a Write recovery time before read T12b Read recovery time before write T12c Consecutive same commands interval T9 T11 T10 T2 T5 Valid T7 DESCRIPTION - 34 - W89C926 PENTIC+ T3 T12 Valid MIN. MAX ...
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... T11 HA0-16, REG hold valid from OE, WE deasserted T12 HA0-16, REG setup to WE deasserted T19 REG low T12 T15 T13 T16 T14 T17 Valid T4 T5 Valid DESCRIPTION - 35 - W89C926 PENTIC+ T11 T10 T18 T7 T6 MIN. MAX. UNIT 150 nS ...
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... Note: These timings are specified when the PENTIC+ does not assert WAIT . Common Memory Access HA0-16 REG CE1 WAIT HD0-15 (Read) HD0-15 (Write) DESCRIPTION T16 REG high T11 T12 T13 T14 Valid T4 Valid - 36 - W89C926 PENTIC+ MIN. MAX. UNIT 180 - nS 150 - nS - 300 nS - 300 300 - nS 250 ...
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... HA0-16, REG setup to WE deassert T12 CE1 ,2 assert to WE deassert T13 WE pulse width T14 WAIT pulse width T15a OE deassert to next WE assert T15b WE deassert to next OE assert T16a Read cycle time T16b Write cycle time DESCRIPTION - 37 - W89C926 PENTIC+ MIN. MAX. UNIT ...
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... WAIT INPACK HDn (Read) T12 HDn (Write) MSAn RCS MSRD MSDn (Read) MSWR MSDn (Write T11 T19 Even Address T20 T21 T24 - 38 - W89C926 PENTIC+ T14 T15 T28 T16 T17 T18 T9 T10 T13 Odd Address T23 T22 T25 T27 T26 ...
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... T15a OE, WE deasserted to CE1 ,2 deasserted. T15b IORD, IOWR deasserted to CE1 ,2 deasserted. T16a OE, WE deasserted to HA0-16 deasserted. DESCRIPTION Note 2 Note 3 Note 4 Note 1 Note 8 Note 6 Note 9 Note 1, 5 Note 1, 5 Note 7 Note W89C926 PENTIC+ MIN. MAX. UNIT ...
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... REG is asserted for I/O access and it is deasserted for common memory access. 8. INPACK is asserted only for I/O read operation. 9. This is a shared memory access without bus contention. 10. This is the timing for SRAM-15. DESCRIPTION Note 4 Note 1 Note 2 Note.10 Note 1 Note.10 Note. W89C926 PENTIC+ MIN. MAX. UNIT ...
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... Nonvolatile memory auto-load time T5 Flash memory auto-reading recovery time T6 SRAM image auto-writing recovery time T7 EEPROM auto-reading recovery time EECS/FCS floating Auto-Loading T5 T7 SRAM Write even byte - 41 - W89C926 PENTIC+ T5 Flash Memory Loading T6 T6 SRAM Write odd byte MIN. MAX. UNIT 500 - nS 400 - nS 20 ...
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... MSD2 clock period T6 MSD1 set up time to MSD2 high T7 MSD1 hold time from MSD2 high T8 MSD0 valid from MSD2 high AUI Transmit Timing (End of Transmit) TX+/- TX+/- DESCRIPTION W89C926 PENTIC+ T2 MIN. MAX. 500 0 - 500 - 500 - 1 - 500 - 500 - 500 T TOI 0 ...
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... T LPW TXO+ TXO- SYMBOL DESCRIPTION Link Output Pulse Interval T LPI T Link Output Pulse Width LPW DESCRIPTION T LPI - 43 - W89C926 PENTIC+ MIN. MAX. 200 8000 T EOP1 T EOP0 MIN. MAX. 200 200 MIN. MAX 120 Publication Release Date: January 1996 Revision A1 ...
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... Input Waveform Level (Diff) Input and Output Waveform Reference Levels (Diff) 3-State Reference Levels Note: The above specifications are valid only if the mandatory isolations are properly employed and all differential signals are taken to the AUI of the pulse transformer. W89C926 PENTIC ...
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... Output timing is measured with a purely capacitive load 240 pF. The following correction factor can be used for other loads (this factor is preliminary): Derating for 3SL, MOS = -0.05 nS/pF Derating for 3SH, OCL, TPI = -0.03 nS/pF SW1 (Note 3) DEVICE UNDER TEST PARAMETER - 45 - W89C926 PENTIC 2.2K Output CL (Note 1, 2) TYP UNIT ...
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... Note: In the above diagram, the TX+ and TX- signals are taken from the AUI side of the pulse transformer. The pulse transformer used for all testing is a 100 H +/-0.1% Pulse Engineering PE64103. UTP Transmit Test Load TXO+ TXO- Note: In the above diagram, the UTP filter used for all testing is a Valor FL1012 1.21K 1% UTP FILTER - 46 - W89C926 PENTIC 100 1% ...
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... PACKAGE DIMENSIONS The PENTIC+ is packaged in a 100-pin TQFP for type II PC card applications. Detailed dimensions are shown below W89C926 PENTIC W89C926F e b Symbol Dimensions in inches Dimensions 0.004 +/- 0.002 A2 0.055 +/- 0.002 b 0.013 + 0.002 - 0.004 C 0.008 max 0.004 min D 0 ...
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... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. W89C926 PENTIC+ Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...