cxd2589q Sony Electronics, cxd2589q Datasheet - Page 33

• Manufacturer Part Number: cxd2589q
• Description: Cd Digital Signal Processor
• Manufacturer: Sony Electronics

1-2. Description of SENS Output
2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2589Q.
Sub Q can be read out after checking the CRC of the 80bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
2-1. P to W Subcode Readout
2-2. 80-bit Sub Q Readout
Microcomputer serial
register value
(latching not required)
$0X, 1X, 2X, 3X
$4X
$5X
$6X
$AX
$EX
$7X, 8X, 9X, BX, DX, FX
$CX
The following signals are output from SENS, depending on the microcomputer serial register value (latching
not required).
Note that the SENS output can be read out from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.
(See the $BX commands.)
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80bits are
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
• The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration
• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
• The high and low intervals for SQCK should be between 750ns and 120µs.
check circuit.
loaded into the parallel/serial register.
When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this
interval, the serial/parallel register is not loaded into the parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
SENS
output
SEIN
XBUSY
FOK
SEIN
GFS
OV64
“L”
CNIN
division
SEIN, a signal input to this LSI from the SSP, is output.
Low while the auto sequencer is in operation, high when operation
terminates.
Outputs the signal input to the FOK pin. Normally, FOK (from RF) is
input. High for "focus OK".
SEIN, a signal input to this LSI from the SSP, is output.
High when the regenerated frame sync is obtained with the correct timing.
Low when the EFM signal, after passing through the sync detection
filter, is lengthened by 64 channel clock pulses or more.
SENS pin is fixed to low.
Calculates the number of tracks from the frequency division ratio set
by $B.High when $C is latched; toggles each time CNIN is input the
number of times set in register B.
– 33 –
Meaning
CXD2589Q