cxd2589q Sony Electronics, cxd2589q Datasheet - Page 54

• Manufacturer Part Number: cxd2589q
• Description: Cd Digital Signal Processor
• Manufacturer: Sony Electronics

5. 1bit DAC Block
5-1. DAC Block Input Timing
5-2. Description of DAC Block Functions
Timing Chart 5-1 shows the input timing for the DAC block.
Audio data is not transferred from the CD signal processer block to the DAC block inside the CXD2589Q.
This is to allow data to be sent to the DAC block via the audio DSP, etc.
When data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI and
PCMDI, respectively.
Zero data detection
When the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for approximately 300ms, zero data is detected. Zero data detection is performed
independently for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected by the ZDPL command of $9X.
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and
Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then
approaches Y3 from the value (B or C in the figure) at that point.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
7F (H)
0dB
– 54 –
23.2 [ms]
A
Y1
B
Y3
C
Y2
–
00 (H)
CXD2589Q