80C196MD INTEL [Intel Corporation], 80C196MD Datasheet - Page 16

• Manufacturer Part Number: 80C196MD
• Description: 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
• Manufacturer: INTEL [Intel Corporation]

8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
16
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
PACT#
PALE#
PBUS.15:8
PBUS.7:0
PMODE.3
PMODE.2
PMODE.1
PMODE.0
PROG#
PVER
PWM1:0
RD#
Signal
Name
Type
I/O
O
O
O
O
O
I
I
I
Port 6. This is an 8-bit output port that is multiplexed with the
special functions of the waveform generator and PWM
peripherals. The WG_OUT register configures the pins,
establishes the output polarity, and controls whether changes
to the outputs are synchronized with an event or take effect
immediately.
Programming Active. In auto-programming mode, PACT#
low indicates that programming activity is occurring.
Programming ALE. In slave programming mode, this active-
low input indicates that ports 3 and 4 contain a
command/address. When PALE# is asserted, data and
commands on ports 3 and 4 are read into the device.
Programming Bus. In programming modes, used as a
bidirectional port with open-drain outputs to pass commands,
addresses, and data to or from the device. Used as a regular
system bus to access external memory during auto-
programming mode. When using slave programming mode,
the PBUS is used in open-drain I/O port mode (not as a
system bus). In slave programming mode, you must add
external pull-up resistors to read data from the device during
the dump word routine.
Programming Mode Select. Determines the OTPROM
programming algorithm that is to be performed. PMODE is
sampled after a device reset when EA# = V
stable while the device is operating.
Programming Start. This active-low input is valid only in
slave programming mode. The rising edge of PROG# latches
data on the PBUS and begins programming. The falling edge
of PROG# ends programming.
Program Verification. In programming modes, this active-
high output signal is asserted to indicate that the word has
programmed correctly. (PVER low after the rising edge of
PROG# indicates an error.)
Pulse Width Modulator Outputs. These are PWM output
pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
Read. Read-signal output to external memory. RD# is
asserted only during external memory reads.
Table 7. Signal Descriptions (Continued)
Description
EA
and must be
PWM1
PWM0
WG3
WG3#
WG2
WG2#
WG1
WG1#
P2.5/COMP1
P2.1/SCLK0#/BCLK0
P4.7:0/AD15:8
P3.7:0/AD7:0
P0.7/ACH7/T1DIR
P0.6/ACH6/T1CLK
P0.5/ACH5
P0.4/ACH4
P2.2/EPA1
P2.0/EPA0
P6.7:6
P5.3
Multiplexed
With
®