gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 12
gc41c501g0-sp8i
Manufacturer Part Number
gc41c501g0-sp8i
Description
4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G0-SP8I.pdf
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P0[2:0]
P2[2:0]
Symbol
5. Pin Description (8-pin)
V
V
DD
SS
Input/Output
Input/Output
Direction
Power
Power
Power Supply
Ground
Parallel Input/Output port.
Schmitt Trigger input and open-drain output with internal pull-up TR.
The STOP mode is released by "L" input of each pin.
Parallel Input/Output port. Each bit can be individually set or cleared.
Schmitt Trigger input and open-drain output with internal pull-up TR.
P2 can be configured as a push-pull output port.
P2[0] and P2[1] are also used for ISP of FLASH memory.
Description
ATOM1.0 Family
Preliminary
Remark
[12]
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