gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 20

• Manufacturer Part Number: gc41c501g0-sp8i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

IOCFG (0Eh) : I/O Port Configuration Register
XI/XO for Clock Input/Output
XI/XO as an I/O Port
IOXEN : Enable XI and XO as I/O ports.
P2OEN : Configure P2 as a push-pull output port .
IOMAP[1:0] : Configure I/O ports mapping .
6.5. I/O Ports : PORT4[1:0] (XI/XO)
IOMAP1
IOMAP1
R/W(0)
0
0
1
1
Enabled if XT/RG bit in CKCFG SFR is set.
Disabled in STOP mode (XI and XO are in low state).
XI and XO can be configured as I/O port if IOXEN bit in
IOCFG SFR is set.
User should not set XT/RG and IOXEN at the same time.
Pull-up enable and input by default (reset).
Open drain active low output.
CPU always write to SFR register, but reads port pin.
Retains the previous state at stop mode.
0 = XI and XO are used for clock input (Default).
1 =
IOMAP0
XI and XO is used for PORT4[1:0]
0
1
0
1
IOMAP0
R/W(0)
Optional 20-pin I/O Port Mapping
Optional 24-pin I/O Port Mapping
R/W(0)
P2OEN
Ports Mapping
Reserved
Default.
.
R/W(0)
IOXEN
CPU Write
CPU Write
CPU Read
CPU Read
IOCFG
This SFR is initialized to default state only by power-on-
reset. Only the P2OEN bit is cleared by other resets.
For 8-pin devices, only P2OEN bit is available. User
should not set other bits.
P4.0
P4.1
SFR
SFR
QB
QB
Q
Q
IOXEN
30 KΩ
30 KΩ
ATOM1.0 Family
Preliminary
500 KΩ
XT/RG
[20]
XI
/ P4.0
XO
/ P4.1