ade3800 STMicroelectronics, ade3800 Datasheet - Page 59

• Manufacturer Part Number: ade3800
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions With Embedded Lvds And Rsds Transmitters
• Manufacturer: STMicroelectronics

ADE3800
Note:
4.11 Pattern Generator (PGEN)
Note:
4.11.1 Overview
H_KERNEL_1
H_KERNEL_2
H_KERNEL_3
H_KERNEL_4
H_KERNEL_5
H_KERNEL_6
H_KERNEL_7
H_KERNEL_8
H_KERNEL_NORM
V_KERNEL_0
V_KERNEL_1
V_KERNEL_2
V_KERNEL_3
V_KERNEL_4
V_KERNEL_NORM
Register
Upscaling and downscaling can be simultaneously combined horizontally and vertically.
The PGEN block can generate graphic patterns to support debug and test tasks for LCD panels
such as horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color
scales. It is also possible to pass through the RGB signal coming from the SCL block.
The PGEN block is located before the sRGB color management block.
The following features of the PGEN block overlap each other like layers, defining display priorities:
Bars and cells are freely programmable in size and independently of each other.
A border is a horizontal or vertical borderline. If enabled, it has priority over the above settings.
Above all, aTCON window, if enabled, restrains all PGEN settings to a given display area.
●
●
●
●
Bars (lowest display priority)
Cells and Grids
Borders
TCON Window Control (highest display priority)
0A11
0A12
0A13
0A14
0A15
0A16
0A17
0A18
0A19
0A1A
0A1B
0A1C
0A1D
0A1E
0A1F
Address
00
00
00
00
00
20
40
40
40
00
00
00
00
00
40
Nearest Neighbor
No Scaling
00
00
00
00
10
20
30
40
40
00
00
00
10
20
40
Down Scaling
Bilinear
Register Description by Block
FE
FA
F9
FF
10
26
39
41
40
FB
F9
FF
10
23
40
“-0.7” Cubic
Up Scaling
FE
FC
FB
00
0F
24
38
40
40
FA
FA
FE
0D
22
40
“-0.5” Cubic
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