bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 130

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.2 Global Control and Status Registers
JAUTO
JCENTER
JSIZE[2:0]
3-12
Enable JCLK Acceleration—When active, the jitter attenuated output clock (JCLK) phase is
accelerated (added or subtracted) if the elastic store depth is within 1 Unit Interval (UI) of its
limit. JCLK frequency is increased if the depth is within 1 UI of overflow, or decreased if the
depth is within 1 UI of under-run. JAUTO does not affect JAT operation during other depth
conditions. The amount of JCLK acceleration is proportional to the proximity of the elastic
store limit, quantized in 0.125 UI steps. The JCLK phase is accelerated in 5 ns increments for
each quantized step, to a total of 40 ns (maximum 0.08 UI output jitter). JAUTO expands the
JAT loop bandwidth during near-limit conditions and allows JCLK to remain
frequency-locked during an instantaneous reference clock switchover. Clock acceleration ( )
is reported in CKERR interrupt [addr 006] and CPDERR [addr 021] status. JAUTO cannot
prevent elastic store data errors [JERR; addr 006] if an invalid, out-of-frequency range clock is
applied on the JAT reference input. If JCLK is programmed to free-run (JFREE), the processor
must disable JAUTO. The processor can optionally disable JAUTO to prevent unnecessary
clock acceleration when JCLK references CLADI, or during RLOS, RALOS, or TLOC error
conditions.
Force JAT to Center (not auto clear)—Writing a 1 and then a 0 to JCENTER resets the elastic
store write pointer and forces the elastic store read pointer to 1-half the programmed JSIZE.
The processor writes JCENTER at power-up. Depending upon which JAT reference is
selected, the processor can optionally assert JCENTER after recovery from a loss of signal
(RLOS or RALOS) or in response to a transmit loss of clock (TLOC), or after recovering from
a persistent clock error (CKERR).
JAT Elastic Store Size—Selects the maximum depth of JAT elastic store. The 32-bit depth is
sufficient to meet jitter attenuation requirements in all cases where JAT cutoff frequency is
programmed at 6 Hz and the selected clock reference is frequency-locked. However, in cases
where an external reference is selected or a narrow loop bandwidth is programmed, the elastic
store depth can tolerate up to 64 Unit Intervals (128 bits) of accumulated phase offset.
JSIZE
000
001
010
011
1xx
0 = no acceleration
1 = enable JCLK acceleration
0 = normal operation
1 = recenter JAT elastic store
Elastic Store Size
Conexant
128 Bits
16 Bits
32 Bits
64 Bits
8 Bits
Fully Integrated T1/E1 Framer and Line Interface
Bt8370/8375/8376
N8370DSE