bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 137

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
All count overflow events in ISR4 are caused by rising edge sources. Each event is latched active-high when the
respective error counter [addr 050–05A] reaches its maximum count value, but only while the respective IER4
[addr 00F] interrupt enable bit is active. If the corresponding interrupt is masked, no overflow status is reported.
Active overflow status bits are held until the processor read clears ISR4. Each event triggers an interrupt if the
corresponding IER4 bit is enabled.
FRED[4]
COFA[2]
SEF[2]
BERR[12]
FEBE[10]
LCV[16]
CRC[10]
FERR[12]
All events in ISR3 are caused by rising edge sources. Each event is latched active-high and held until the
processor read clears ISR3. Each event triggers an interrupt if corresponding IER3 bit is enabled [addr 010].
TSIG
TMSYNC
TMF
TFRAME
N8370DSE
007— Counter Overflow Interrupt Status (ISR4)
008— Timer Interrupt Status (ISR3)
FRED[4]
TSIG
7
7
Out of Frame Error Count Overflow
Change of Alignment Count Overflow
Severely Errored Frame Count Overflow
Test Pattern Bit Error Count Overflow
FEBE Error Count Overflow
LCV (BPV+EXZ) Error Count Overflow
CRC6/CRC4 Error Count Overflow
Ft/Fs/FPS/FAS Error Count Overflow
Transmit Signaling Multiframe—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms
(CAS), coincident with the first bit of a transmit signaling multiframe.
TX System Bus MF Sync—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (CAS),
coincident with the first bit of transmit system bus multiframe input on TPCMI.
Transmit Multiframe—TMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF, Ft), or 2 ms
(MFAS), coincident with the first bit of a transmit multiframe.
Transmit Frame—Activated every 193 bits (T1) or 256 bits (E1), coincident with first bit of a
transmit frame. The processor can read TPHASE [addr ODC] to determine which TSLIP
buffer half can be accessed.
TMSYNC
COFA[2]
6
6
SEF[2]
TMF
5
5
0 = no timer event
1 = transmit signaling multiframe
0 = no timer event
1 = TSB multiframe
0 = no timer event
1 = transmit multiframe
0 = no timer event
1 = transmit frame
BERR[12]
TFRAME
4
4
Conexant
FEBE[10]
RSIG
3
3
RMSYNC
LCV[16]
2
2
3.4 Interrupt Status Registers
CRC[10]
RMF
1
1
3.0 Registers
FERR[12]
RFRAME
0
0
3-19