mh89760b Mitel, mh89760b Datasheet - Page 23

• Manufacturer Part Number: mh89760b
• Description: St-bus? Family T1/esf Framer & Interface
• Manufacturer: Mitel

Preliminary Information
connecting the frame pulse output, F0o, of PLL #2 to
F0i of PLL # 1, the MT8941 will generate the T1
transmit clock that is phase-locked to F0o, which in
turn is phase-locked to the master synchronization
signal, E8Ko. If all of the T1 trunks are from the
network any short term differences in the received
data rate will be absorbed by the elastic buffer in the
MH89760B.
6. Digital Multiplex Interface (DMI)
Figure 16 illustrates an implementation of the Digital
Multiplex Interface (DMI) specification, which defines
a computer to PBX interface. This interface can
convert 300 baud to 64 kbaud asynchronous or
synchronous data channels to T1 format with clear
channel capabilities and common channel signalling.
Figure 16 is broken down into four functional blocks
which are the asynchronous interface (ACIAs), the
R
S
2
3
2
R
S
2
3
2
R
S
2
3
2
Asynchronous
Interface
•
•
•
ACIA
ACIA
ACIA
D
D
D
A
A
A
0
0
0
0
0
0
-D
-D
-A
-D
-A
-A
7
7
7
7
7
7
•
•
•
•
•
Micro
68008
Protocol Converter
•
Figure 16 - Digital Multiplex Interface (DMI)
•
•
•
•
D
A
D
D
A
A
0
0
MT8952
MT8952
0
0
0
0
MT8952
-D
-A
-D
-D
-A
-A
•
•
•
•
7
7
7
7
7
7
•
• •
• •
•
•
•
protocol converter (micro and MT8952s), the switch
matrix (MT8980), and the T1 interface (MH89760B).
The
Adapters (ACIA) provide a standard RS232 interface
that is compatible with many off-the-shelf modems
and data sets. A single microprocessor is capable of
handling the protocol conversion between the RS232
ports and the MT8952 HDLC protocol controller.
The MT8952 interfaces directly to the ST-BUS, which
in turn interfaces directly to the T1 interface devices.
Instead of the MT8952 operating at 64 kbit/s
continuously, it operates at 2.048 Mbit/s and
inputs/outputs an 8 bit burst every 125 µsec. This
feature eliminates the need for an additional rate
conversion circuit to multiplex the HDLC outputs up
to the T1 data rate. Each of the HDLC chips is
assigned a timeslot on the ST-BUS in a manner that
is similar to enabling a voice codec. When the
MT8952 is not enabled the output driver is tristated.
Switch Matrix
STi0
STo0
F0i
C4i
MT8980
Asynchronous
C1.5i
F0i
C4i
STo1
STo2
C2i
STo3
STi1
STi2
•
DSTi
DSTo
CSTi0
CSTo
CSTi1
C2i
C1.5i
F0i
CVb
F0i
F0b
C4b
C20
MT89760B
MT8941
DPLL #1
DPLL #2
Communications
T1 Interface
OUTA
OUTB
C8Kb
E8Ko
C12i
RxR
RxT
MH89760B
16.384
12.352
MHz
Osc.
MHz
Osc.
Equal-
Interface
izer
4-77