ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 18

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST18-AU1
HSR: Host status register
All bits are reset when the register is read. The register can only be read by the D950.
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HTIEN
STOPIEN
ACKFIEN
BERRIEN
-
Bit
BUSY
DATADIR
HDRWRQ
HDRRRQ
STOP
ACKFAIL
BERR
-
15
-
14
-
13
-
Transfer interrupt enable
Stop interrupt enable
Acknowledge fail interrupt
Bus error interrupt
RESERVED, read as 0.
Function
Set when Valid slave address detected, until Stop event or Restart event with invalid slave
address.
Data direction (valid when Busy bit is set).
HDR write request. Set when data is required by the host. Data needs to be written into
the HDR register, this is reset when the HSR register is read.
Host read request. Set when data has been sent by the host. Data needs to be read from
the HDR register, this is reset when the HSR register is read.
Stop. Set when a stop condition is detected.
Acknowledge fail. Set when the host does not generate an acknowledge after one data
byte has been sent.
Bus error. Set when a misplaced start or stop condition is detected during transmission.
RESERVED, read as 0.
BERR ACK-
12
0
1
0
1
0
1
0
1
0
1’
FAIL
11
transfer interrupt disabled
transfer interrupt enabled
stop interrupt disabled
stop interrupt enabled
acknowledge fail interrupt disabled
acknowledge fail interrupt enabled
bus error interrupt disabled
bus error interrupt enabled
receive data from host
send data to host
STOP HDRR
10
RQ
9
HDRW
RQ
8
7
-
6
-
5
-
4
-
3
-
2
-
ADIR
DAT-
1
BUSY
0