ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 35

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 8.1
8.1 Interrupt controller registers
The interrupt controller interface is controlled by status and control registers mapped into the
Y-memory space. Status registers are not write-protected.
IVO0-7: Interrupt vector0-7 address registers
The IVO0-7 registers contain the first address of the interrupt routine and are associated with
the respective interrupt input ITRQ, see Table 8.1. The register content of the interrupt under
service is provided on the YD bus during the cycle following the ITACK falling edge.
(Address = 0020-0027, No reset value, Read/Write)
ICR: Interrupt control register
The ICR register displays the current priority level and up to four stacked priority levels.
(Address = 0028, Reset = 000Bh, Read/Write))
IVi15
15
15
SPL4 (2:0)
14
IVi14 IVi13 IVi12
14
13
D950Core interrupt controller
D950Core
13
12
SPL3 (2:0)
12
11
INCYCLE
IVi11 IVi10 IVi9 IVi8 IVi7 IVi6 IVi5 IVi4 IVi3 IVi2 IVi1 IVi0
11
ITACK
YWR
10
YRD
EOI
IT
10
9
SPL2 (2:0)
16
16
9
8
8
7
IT
ITACK
EOI
YWR
YRD
CLK
7
6
SPL1 (2:0)
CONTROLLER
PERIPHERAL
6
INTERRUPT
RESET
5
5
4
AS-DSP
4
ES
3
YD
YA
3
VR02020C
2
ITRQ0
ITRQ1
ITRQ2
ITRQ3
ITRQ4
ITRQ5
ITRQ6
ITRQ7
2
CPL (2:0)
ST18-AU1
1
1
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0
0