alc260d-ve-lf Realtek Semiconductor Corporation, alc260d-ve-lf Datasheet
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... ALC260/ALC260D Series 2 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET Rev. 1.4 15 August 2005 Track ID: JATR-1076-21 ...
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... This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC260(D) audio codec chip ...
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GENERAL DESCRIPTION................................................................................................................................................1 2. FEATURES...........................................................................................................................................................................2 2. ....................................................................................................................................................2 ARDWARE EATURES 2. .....................................................................................................................................................3 OFTWARE EATURES 3. SYSTEM APPLICATIONS ................................................................................................................................................3 4. BLOCK DIAGRAM.............................................................................................................................................................4 4. ............................................................................................................................................................4 LOCK IAGRAM 4. NALOG NPUT UTPUT 5. PIN ...
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Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) .............................27 8.1.13. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)............................................................27 8.1.14. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) ......................................................28 8.1.15. Parameter – Processing Capabilities (Verb ID=F00h, ...
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Link Reset and Initialization Timing ....................................................................................................................66 9.2.2. Link Timing Parameters at the Codec ..................................................................................................................67 9.2.3. S/PDIF Output and Input Timing .........................................................................................................................68 9.2.4. Test Mode .............................................................................................................................................................68 9. ...............................................................................................................................................69 NALOG ERFORMANCE 10. APPLICATION CIRCUITS..........................................................................................................................................70 11. MECHANICAL DIMENSIONS ...................................................................................................................................71 12. ...
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T 36. V – ABLE ERB ET ONNECTION T 37. V – ABLE ERB ET ONNECTION T 38. V – ABLE ERB ET OEFFICIENT T 39. V – ABLE ERB ET OEFFICIENT ...
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..........................................................................................................................................................4 IGURE LOCK IAGRAM IGURE NALOG NPUT UTPUT ........................................................................................................................................................5 IGURE IN SSIGNMENTS F 4. HDA L P ..................................................................................................................................................8 IGURE INK ROTOCOL ...................................................................................................................................................................9 IGURE ...
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... General Description The ALC260 and ALC260D* 2-Channel High Definition Audio (HDA) Codecs with UAA (Universal Audio Architecture), featuring a 24-bit two-channel DAC and two stereo 20-bit ADCs, are designed for commercial Desktop and Notebook PC systems. The codecs incorporate proprietary converter technology to achieve 95dB sound quality; easily meeting PC2001 requirements and also bringing PC sound quality closer to consumer electronic devices ...
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Features 2.1. Hardware Features Single-chip multi-bit Sigma-Delta converters with high S/N ratio 1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192kHz sample rate 2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96kHz sample rate Applicable for 2-Channel 192kHz DVD-Audio ...
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... Enhanced Configuration Panel and device sensing wizard to improve user experience Content Copy Protection for S/PDIF interface Power Management setting Microphone Acoustic Echo Cancellation (AEC) and Beam Forming (BF) technology for voice application Mono/Stereo Microphone Noise Suppression ALC260D, ALC260D-LF, ALC260D-VE, and ALC260D-VE-LF feature Dolby Digital Live 3. System Applications Multimedia PCs 3D PC Games ...
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Block Diagram 4.1. Block Diagram ALC260(D) - High Definition Audio (HDA) Codec RESET# BITCLK SYNC SDOUT SDIN HDA Link Interface 1 : Stereo Analog Parameters : Stereo Digital VOL: Analog Volume M: Analog Mute 1Ah Vendor Regs. 4.2. Analog ...
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Pin Assignments MONO-OUT AVDD2 HP-OUT-L JDREF HP-OUT-R AVSS2 GPIO0 GPIO1 NC NC SPDIFI/EAPD SPDIFO Note: JDREF is used to calibrate reference current for jack detection. 5.1. Package and Version Identification Lead (Pb)-free package is indicated by an ‘L’ in ...
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Pin Descriptions 6.1. Digital I/O Pins Name Type Pin # RESET SYNC I 10 BITCLK I 6 SDATA-OUT I 5 SDATA- SPDIFI / I/O 47 EAPD SPDIFO O 48 GPIO0 I/O 43 GPIO1 I/O 44 ...
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Name Type Pin # LINE-OUT LINE-OUT HP-OUT HP-OUT MONO-OUT O 37 Sense Sense DCVOL I 33 6.3. Filter/Reference Name Type Pin # VREF - 27 MIC1-VREFO-L ...
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High Definition Audio Link Protocol 7.1. Link Signals The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz ...
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Signal Definitions Item Description BCLK 24.0MHz bit-clock sourced from the HDA controller and connecting to all codecs. SYNC 48kHz signal is used to synchronize input and output streams on the link sourced from the HDA controller and ...
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Signaling Topology The HDA controller supports two SDOs for the outbound stream SDIs for the inbound stream. RST#, BCLK, SYNC, SDO0 and SDO1 are driven by the controller to codecs. Each codec drives its own point-to-point ...
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Frame Composition 7.2.1. Outbound Frame – Single SDO An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in ...
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Inbound Frame – Single SDI An Inbound Frame – Single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each ...
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Variable Sample Rates The HDA link is designed for sample rates of 48kHz. Variable sample rates are delivered in multiple or sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate. One sample block ...
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Table 9. 44.1kHz Variable Rate of Delivery Timing Rate Delivery Cadence 11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat 88.2kHz 12 -11 -11 -12 -11 - 174.4kHz 12 -11 ...
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Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ bit in the Global Control ...
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Codec Reset A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being reset to the default state. After the target codec completes its reset operation, an initialization sequence is requested. 7.3.3. ...
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Verb and Response Format 7.4.1. Command Verb Format There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the ...
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Power Management The ALC260(D) does not support Wake-Up events when in low-power mode. All power management state changes in widgets are driven by software. Table 14 shows the System Power State Definitions. In the ALC260(D), only the audio function ...
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Supported Verbs and Parameters This section describes the Verbs and Parameters supported by various widgets in the ALC260(D verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’. Refer to Figure ...
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Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) Table 20. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) Codec Response Format Bit Description 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA ...
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Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) Table 22. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) Codec Response Format Bit Description 31:9 Reserved. Read as 0’s. 8 UnSol Capable. 0: Unsolicited response is not supported ...
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Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) Table 24. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) Codec Response Format Bit Description 31:24 Reserved. Read as 0’s. 23:20 Widget Type. 0h: Audio Output 1h: Audio Input ...
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Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) Provides default information about formats. Individual converters have their own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 25. Parameter – Supported PCM Size, ...
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Codec Response Format Bit Description 6 R7. 48kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz rate. 5 R6. 44.1kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz ...
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Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table ...
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Codec Response Format Bit Description 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. Uses dedicated Jack-Detect pins to detect when a jack is plugged in. 1 Trigger Required. ‘1’ indicates whether ...
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Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Codec ...
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Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Table 31. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Codec Response Format Bit Description 31:4 Reserved. Read as 0’s. 3 D3Sup. 1: Power state D3 is supported. 2 ...
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Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Table 33. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0. GPIO wake up function not supported. 30 GPIUnsol=1. GPIO unsolicited response not supported. 29:24 ...
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Verb – Get Connection Select Control (Verb ID=F01h) Table 35. Verb – Get Connection Select Control (Verb ID=F01h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F01h Codec Response for NID=04h (MIC ADC) Bit Description 31:8 ...
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Codec Response for NID=0Ch (MIC2 Selector) Bit Description 31:8 0’s. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved Codec Response for NID=0Dh (LINE1 Selector) Bit Description 31:8 ...
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Verb – Set Connection Select (Verb ID=701h) Table 36. Verb – Set Connection Select (Verb ID=701h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=701h Note: See section 8.2 Verb – Get Connection Select Control (Verb ...
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Codec Response for NID=05h (MIX ADC) Bit Description 31:24 Connection List Entry (N+3). Return 15h (=27, Pin Complex - LINE2) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for n>7. 23:16 Connection List Entry (N+2). Return 14h (Pin ...
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Codec Response for NID=08h (LOUT1 Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry ...
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Codec Response for NID=0Bh (MIC1 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection ...
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Codec Response for NID=0Eh (LINE2 Sel) Bit Description 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum ...
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Codec Response for NID=13h (Pin Widget: MIC2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Ch (MIC2 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=14h (Pin ...
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Verb – Get Coefficient Index (Verb ID=Dh) Table 38. Verb – Get Coefficient Index (Verb ID=Dh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=20h (Realtek Defined Hidden Registers) Bit Description 31:16 Reserved. Read ...
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Verb – Get Processing Coefficient (Verb ID=Ch) Table 40. Verb – Get Processing Coefficient (Verb ID=Ch) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=20h (Realtek Defined Hidden Registers) Bit Description 31:16 Reserved. Read ...
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Verb – Get Amplifier Gain (Verb ID=Bh) This verb is used to get gain/attenuation settings from each widget. Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh ‘Get’ Payload in Command Bit[15:0] Bit Description 15 Get Input/Output. 0: ...
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Codec Response for NID=08h~0Ah (Sum Widget: LOUT1, LOUT2, MONO Sum) Bit Description 31:8 0’s. 7 Bit- ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute Bit- ‘Get Amplifier Gain’: Read as 0 (No ...
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Verb – Set Amplifier Gain (Verb ID=3h) This verb is used to set amplifier gain/attenuation in each widget. Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh ‘Set’ Payload in Command Bit[15:0] Bit Description 15 Set Output Amp. ...
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Verb – Get Converter Format (Verb ID=Ah) Table 44. Verb – Get Converter Format (Verb ID=Ah) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=02h, 03h (Output Converters: DAC and S/PDIF-OUT) Codec Response for ...
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Verb – Set Converter Format (Verb ID=2h) Table 45. Verb – Set Converter Format (Verb ID=2h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh ‘Set’ payload in command Bit [15:0] Bit Description 31:16 Reserved. Read as 0. ...
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Codec Response for NID=01h (Audio Function Group) Bit Description 3:2 Reserved. Read as 0’s. 1:0 PS-Set, Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 ...
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Verb – Get Converter Stream, Channel (Verb ID=F06h) Table 48. Verb – Get Converter Stream, Channel (Verb ID=F06h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F06h Codec Response for NID=02h, 03h (Output Converters: DAC and ...
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Verb – Get Pin Widget Control (Verb ID=F07h) Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F07h Codec Response for NID=0Fh, 10h, 11h, 12h, 13h, 14h, ...
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Verb – Set Pin Widget Control (Verb ID=707h) Table 51. Verb – Set Pin Widget Control (Verb ID=707h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=707h ‘Pin Control’ in command [7:0]: (Pin: LINE-OUT, HP-OUT, MONO-OUT, ...
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Verb – Get Unsolicited Response Control (Verb ID=F08h) Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an unsolicited response to inform software of a real-time event. Table 52. Verb – Get ...
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Verb – Set Unsolicited Response Control (Verb ID=708h) Enables a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=708h ‘EnableUnsol’ ...
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Verb – Execute Pin Sense (Verb ID=709h) Table 55. Verb – Execute Pin Sense (Verb ID=709h) Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID= 709h ‘Payload’ in Command Bit [7:0] for NID=0Fh, 10h, 12h~15h Bit Description ...
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Verb – Set Configuration Default Bytes (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and 1Eh~1Fh such as placement and ...
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Verb – Set BEEP Generator (Verb ID=70Ah) Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=71Bh ‘Divider’ in Set Command Bit Description 31:8 Reserved. 7:0 Frequency ...
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Verb – Set GPIO Data (Verb ID= 715h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=715h ‘Data’ in Set command for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] (not supported). 3:0 ...
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Verb – Set GPIO Enable Mask (Verb ID=716h) Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=716h Codec Response for NID=01h (Audio Function Group) Bit Description ...
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Verb – Set GPIO Direction (Verb ID=717h) Table 65. Verb – Set GPIO Direction (Verb ID=717h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=717h Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. ...
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Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=719h Codec Response for NID=01h (Audio ...
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Verb – Get Digital Converter Control (Verb ID= F0Dh) Table 69. Verb – Get Digital Converter Control (Verb ID= F0Dh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F0Dh NID=03h (S/PDIF-OUT) Response to ‘Get verb’ – ...
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NID=06h (S/PDIF-IN) Response to ‘Get verb (F0Dh)’ Bit Description – S/PDIF-IN Channel Status 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 Reserved. 1 In‘V’alid. V bit in sub-frame ...
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Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit [7:0] 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity ...
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Verb – Get/Set EAPD Enable (Verb ID= F0Ch/70Ch) Table 71. Verb – Get/Set EAPD Enable (Verb ID= F0Ch/70Ch) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID= F0Ch Codec response in Get Command for NID=0Fh (LINE-OUT ...
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Get/Set Volume Knob Widget (NID=1Bh) (Verb ID= F0Fh/70Fh) Table 72. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F0Fh Codec Response for NID=1Bh (Volume Knob Widget) Bit Description ...
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Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0]) (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0]) Set Command Format Bit [31:28] Bit [27:20] ...
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Characteristics 9.1. DC Characteristics 9.1.1. Absolute Maximum Ratings Parameter Power Supplies: Digital Analog Ambient Operating Temperature Storage Temperature All Pins 9.1.2. Threshold Voltage DVDD = 3.3V±5 25°C, with 50pF external load. ambient Parameter Input Voltage Range Low ...
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Digital Filter Characteristics Filter Symbol ADC Lowpass Filter Passband Stopband Stopband Rejection Passband Frequency Response DAC Lowpass Filter Passband Stopband Stopband Rejection Passband Frequency Response 9.1.4. S/PDIF Input/Output Characteristics DVDD= 3.3V, T =25°C, with 75Ω external load. ambient Parameter ...
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AC Characteristics 9.2.1. Link Reset and Initialization Timing Parameter RESET# Active Low Pulse Width RESET# Inactive to BCLK Startup delay for PLL ready time SDI Initialization Request 4 BCLK BCLK SYNC SDO SDI RESET# 2 Channel High Definition Audio ...
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Link Timing Parameters at the Codec Parameter BCLK Frequency BCLK Period BCLK Jitter BCLK High Pulse Width BCLK Low Pulse Width SDO Setup Time at Both Rising and Falling Edge of BCLK SDO Hold Time at Both Rising and ...
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S/PDIF Output and Input Timing Parameter *1 S/PDIF-OUT Frequency *1 S/PDIF-OUT Period S/PDIF-OUT Jitter S/PDIF-OUT High Level Width *1 S/PDIF-OUT Low Level Width S/PDIF-OUT Rising Time S/PDIF-OUT Falling Time *2 S/PDIF-IN Period S/PDIF-IN Jitter *2 S/PDIF-IN High Level Width ...
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Analog Performance Standard Test Conditions Parameter Full Scale Input Voltage All Inputs (gain=0dB) All ADC Full Scale Output Voltage All DAC S/N (A Weighted) Analog Inputs to Outputs ADC DAC THD+N Analog Inputs to Outputs ADC DAC Frequency Response ...
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Application Circuits Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design and software driver, Realtek should confirm any modification of application circuits. Realtek may upload the latest application circuits onto our web ...
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Mechanical Dimensions SYMBOL MILLIMETER MIN. TYP MAX. A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC D2 5.50 E 9.00 BSC E1 7.00BSC E2 5.50 b 0.17 0.20 0.27 e ...
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... ALC260-VD-LF ALC260D ALC260D-LF ALC260-VE ALC260-VE-LF ALC260D-VE ALC260D-VE-LF Note 1: See page 5 for lead (Pb)-free package and version identification. Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek sales representatives or agents. Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II, Science Park Hsinchu, 300, Taiwan, R ...