alc850 Realtek Semiconductor Corporation, alc850 Datasheet
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... ALC850 EIGHT CHANNEL AC’97 2.3 AUDIO CODEC DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Rev. 1.4 02 December 2005 Track ID: JATR-1076-21 ...
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... USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC850 Audio codec chip. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process ...
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... MX20 General Purpose Register..........................................................................................................................15 7.1.14. MX24 Audio Interrupt and Paging .......................................................................................................................16 7.1.15. MX26 Power Down Control/Status ......................................................................................................................17 7.1.16. MX28 Extended Audio ID.....................................................................................................................................18 7.1.17. MX2A Extended Audio Status and Control Register.............................................................................................18 Eight Channel AC’97 2.3 Audio Codec Table of Contents V I ERSION DENTIFICATION ..................................................................................................................7 INS ......................................................................................................................7 iii ALC850 Datasheet .............................................................4 Track ID: JATR-1076-21 Rev. 1.4 ...
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... Electrical Characteristics ......................................................................................... 32 8. HARACTERISTICS 8.1.1. Absolute Maximum Ratings ..................................................................................................................................32 8.1.2. Threshold Voltage .................................................................................................................................................32 8.1.3. Digital Filter Characteristics ...............................................................................................................................33 8.1.4. S/PDIF Output Characteristics ............................................................................................................................33 8. IMING HARACTERISTICS 8.2.1. Cold Reset.............................................................................................................................................................33 8.2.2. Warm Reset...........................................................................................................................................................34 8.2.3. AC-Link Clocks.....................................................................................................................................................34 Eight Channel AC’97 2.3 Audio Codec (P ID-00 ) ...............................................................................23 AGE H (P ID-01 ).......................................................................................26 AGE H ..................................................................................................................28 ...................................................................................................................32 ......................................................................................................33 iv ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... T M ....................................................................................................................................44 EST ODE 10.7.1. ATE in Circuit Test Mode......................................................................................................................................44 10.7.2. Vendor Specific Test Mode....................................................................................................................................44 10. OWER FF UNCTION 11. Application Circuits .................................................................................................. 46 12. Mechanical Dimensions ............................................................................................ 47 12. ECHANICAL IMENSIONS 13. Ordering Information ............................................................................................... 48 Eight Channel AC’97 2.3 Audio Codec A ..............................................................................................44 CCESS .....................................................................................................................44 ............................................................................................................45 N .................................................................................................48 OTES v ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Table 28. MX38 Surround Master Volume .................................................................................................21 Table 29. MX3A S/PDIF Output Channel Status and Control....................................................................21 Table 30. S/PDIF Channel Status ................................................................................................................22 Table 31. S/PDIF Validity Control..............................................................................................................22 Table 32. MX60 S/PDIF Input Channel Status [15:0] ................................................................................23 Table 33. MX62 S/PDIF Input Channel Status [29:15] ..............................................................................23 Eight Channel AC’97 2.3 Audio Codec List of Tables vi ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Table 56. AC-Link Low Power Mode Timing ............................................................................................37 Table 57. ATE Test Mode ...........................................................................................................................38 Table 58. AC-Link IO Pin Capacitance and Loading..................................................................................38 Table 59. S/PDIF Output .............................................................................................................................39 Table 60. Analog Performance Characteristics ...........................................................................................40 Table 61. Clocking.......................................................................................................................................42 Table 62. Reset ............................................................................................................................................43 Table 63. Power-Off CD Function Circuitry...............................................................................................45 Table 64. Ordering Information...................................................................................................................48 Eight Channel AC’97 2.3 Audio Codec vii Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ...
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... Figure 6. Signal Rise and Fall Timing.......................................................................................................36 Figure 7. AC-Link Low Power Mode Timing...........................................................................................37 Figure 8. ATE Test Mode Timing .............................................................................................................38 Figure 9. S/PDIF Output............................................................................................................................39 Figure 10. Example of Differential CD Input..............................................................................................43 Figure 11. Power-Down Control .................................................................................................................44 Figure 12. Power-Off CD Function Circuitry..............................................................................................46 Eight Channel AC’97 2.3 Audio Codec List of Figures viii ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... General Description Featuring four 16-bit two-channel DACs and a stereo 16-bit ADC, the ALC850 is an AC’97 Rev 2.3 compatible eight-channel audio codec designed for PC multimedia systems. The ALC850 incorporates proprietary converter technology and fully meets performance requirements for PC99/2001 systems. Four pairs of stereo outputs, with 5-bit volume control and multiple stereo and mono inputs, along with flexible mixing, and gain and mute functions, provide a complete integrated audio solution for PCs ...
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... EAX 1.0 & 2.0 compatible ™ Direct Sound 3D compatible ™ A3D compatible I3DL2 compatible HRTF 3D positional audio 10-band Software Equalizer Voice cancellation and key shifting in Karaoke mode ® AVRack Media Player Configuration Panel for enhanced user experience Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ® ): ...
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... Analog Mixer Diagram Eight Channel AC’97 2.3 Audio Codec MUX Figure 1. Analog Mixer 3 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Lead (Pb)-Free Package and Version Identification Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2. The version number is shown in the location marked ‘V’. Eight Channel AC’97 2.3 Audio Codec Figure 2. Pin Assignments 4 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Schmitt input, V AC'97 master H/W reset Schmitt input, V Crystal selection Internally pulled high by a 100K resistor S/PDIF input/External Amplifier Digital input with 0.4V Schmitt trigger biased at power down control 1.65V/output S/PDIF output Digital output 5 ALC850 Datasheet =0.3Vdd, V =0.4Vdd L H =0.3Vdd, V =0.4Vdd L H =0.3Vdd, V =0.4Vdd ...
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... Trigger point of high Jack Detect 3 Internally pulled high (5V) to AVDD by a 100K resistor. Trigger point of high Jack Detect 4 Internally pulled high (5V) to AVDD by a 100K resistor. Trigger point of high ALC850 Datasheet TOTAL: 25 Pins Track ID: JATR-1076-21 Rev. 1.4 ...
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... AVSS 1nf cap to AVSS Analog output (2.25V – 2.75V) Characteristic Definition Minimum value is 3.0V Maximum value is 5.5V Minimum value is 3.0V Maximum value is 5.5V Minimum value is 3.0V (DVdd-0.3) Maximum value is 3.6V (DVdd+0.3) Minimum value is 3.0V (DVdd-0.3) Maximum value is 3.6V (DVdd+0.3) Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet TOTAL: 5 Pins TOTAL: 8 Pins ...
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... CD4 CD3 CD2 CD1 Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet D0 Default 0 0000h MR0 8000h 8000h X 8000h PH0 8008h MI0 8008h NR0 8808h CR0 8808h AR0 8808h PR0 8808h 0000h 8000h X ...
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... Mute Control 0: Normal 1: Mute (-∞dB) 14:13 - Reserved 12:8 R/W Master Left Volume (ML[4:0]) in 1.5dB steps 7:5 - Reserved 4:0 R/W Master Right Volume (MR[4:0]) in 1.5dB steps For 00h 0dB attenuation MR/ML 1Fh 46.5dB attenuation Eight Channel AC’97 2.3 Audio Codec Table 6. MX00 Reset Table 7. MX02 (Front) Master Volume 9 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... This register controls the input volume for the PC beep signal. Each step in bits 4:1 corresponds to a 3dB increase/decrease in volume. Sixteen levels of volume are available, from 0000 to 1111. The purpose of this register is to allow the PC Beep signals to pass through the ALC850, eliminating the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the Front- Out ...
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... Mute (-∞dB) 14:7 - Reserved 6 R/W 20dB Boost Control 0: Normal 1: 20dB boost 5 - Reserved 4:0 R/W Mic Volume (MV[4:0]) in 1.5dB steps For MV 00h +12dB Gain 08h 0dB attenuation 1Fh -34.5dB Gain Eight Channel AC’97 2.3 Audio Codec Table 10. MX0C PHONE Volume Table 11. MX0E MIC Volume 11 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Mute Control 0: Normal 1: Mute (-∞dB) 14:13 - Reserved 12:8 R/W CD Left Volume (CL[4:0]) in 1.5dB steps 7:5 - Reserved 4:0 R/W CD Right Volume (CR[4:0]) in 1.5dB steps 00h +12dB Gain For CL/CR 08h 0dB attenuation 1Fh -34.5dB Gain Eight Channel AC’97 2.3 Audio Codec Table 12. MX10 LINE_IN Volume Table 13. MX12 CD Volume 12 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Mute Control 0: Normal 1: Mute (-∞dB) 14:13 - Reserved 12:8 R/W PCM Left Volume (PL[4:0]) in 1.5dB steps 7:5 - Reserved 4:0 R/W PCM Right Volume (PR[4:0]) in 1.5dB steps 00h +12dB Gain For PL/PR 08h 0dB attenuation 1Fh -34.5dB Gain Eight Channel AC’97 2.3 Audio Codec Table 15. MX18 PCM_OUT Volume 13 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... LINE LEFT 5 STEREO MIXER OUTPUT LEFT 6 MONO MIXER OUTPUT 7 PHONE For RRS 0 MIC 1 CD RIGHT 2 Mute 3 AUX RIGHT 4 LINE RIGHT 5 STEREO MIXER OUTPUT RIGHT 6 MONO MIXER OUTPUT 7 PHONE Eight Channel AC’97 2.3 Audio Codec Table 16. MX1A Record Select 14 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Reserved 9 - Reserved. Read R/W MIC Select 0: MIC1 1: MIC2 7 R Loop-Back Control 0: Disable 1: Enable 6:0 - Reserved Note: Bit 7 enables ADC to front DAC loop-back. Eight Channel AC’97 2.3 Audio Codec Table 17. MX1C Record Gain Table 18. MX20 General Purpose Register 15 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... This register is used to select a descriptor of 16 word pages between registers MX60 and MX6F. A value used to select vendor specific space to maintain compatibility with the AC’97 2.2 vendor specific register. When PG[3:0] is not 0000b or 0001b, the ALC850 will return zero data for the ACLINK mixer read command Eight Channel AC’ ...
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... Vref Status 1: Vref normal level 0: Not yet 2 R Analog Mixer Status 1: Ready 0: Not yet 1 R DAC Status 1: Ready 0: Not yet 0 R ADC Status 1: Ready 0: Not yet Eight Channel AC’97 2.3 Audio Codec Table 20. MX26 Power Down Control/Status 17 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Function 15:14 R ID[1:0]. Always read as 0 (Only primary ID is supported) 13:12 - Reserved. Read as 0 11:10 R REV [1:0]=10 to indicate that the ALC850 is AC’97 rev. 2.3 compliant 9 R AMAP. Read LDAC. Read as 1 (LFE DAC is supported, in compliance with AC’97 rev. 2. SDAC. Read as 1 (Surround DAC is supported, in compliance with AC’97 rev. 2.3) ...
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... SPACV=1, otherwise S/PDIF output will be all zeros when MX2A.2=1 and SPACV=0 (invalid). 7.1.18. MX2C PCM Front/Center Output Sample Rate Default: BB80H Table 23. MX2C PCM Front/Center Output Sample Rate Bit Type Function 15:0 R Front/Center Output Sample Rate (FOSR) Eight Channel AC’97 2.3 Audio Codec 19 Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ...
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... Center Master Volume (CNT[5:0]) in 1.5dB steps For 00h 0dB LFE/CEN 3Fh 94.5dB attenuation Eight Channel AC’97 2.3 Audio Codec Table 25. MX30 PCM LFE Output Sample Rate Table 26. MX32 PCM Input Sample Rate Table 27. MX36 LFE/Center Master Volume 20 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... PCM data 1: AC3 or other digital non-audio data 0 R Professional or Consumer format (PRO) 0: Consumer format 1: Professional format The ALC850 only supports consumer channel status format. This bit is always 0 Eight Channel AC’97 2.3 Audio Codec Table 28. MX38 Surround Master Volume 21 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... The ‘V’ bit is always 1, and data bits (bit 8 ~ bit 27) should be forced The ‘V’ bit in the sub-frame is always ‘0’, and the S/PDIF output data should be forced CC5 CC6 LEVEL Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ...
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... Type Function 15 R ‘V’ bit in sub-frame of S/PDIFI, S/PDIFI_V 0: Data X and Y are valid 1: At least one of data X and Y is invalid This bit is real-time updated. It indicates that the ALC850 is ready to receive S/PDIF-IN data 14 R S/PDIF-IN Input Signal Locked by hardware, S/PDIFI_LOCK 0: Unlocked 1: Locked 13:12 ...
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... LFE DAC Volume (LD[4:0]) in 1.5dB steps 7:5 - Reserved 4:0 R/W Center DAC Volume (CD[4:0]) in 1.5dB steps For 00h +12dB Gain LD/CD 08h 0dB Gain 1Fh -34.5dB Gain Eight Channel AC’97 2.3 Audio Codec Table 34. MX64 Surround DAC Volume Table 35. MX66 Center/LFE DAC Volume 24 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... MX6A Data Flow Control This register is used to control various parts of the ALC850 multi-channel functions. Default: 0000h Bit Type Function 15 RW SPDIF Input Enable 0: Disable (Default) 1: Enable 14 R/W SPDIF-In Monitoring Control 0: Disable. SPDIFI data is not added into PCM data to DAC (Default) 1: Enable. MSB 16-bit of SPDIFI data will be added into PCM data to DAC if SPDIFI is locked ...
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... This bit sets which jack conductor the sense value is measured from combined with FC[3:0] 0: Tip (Left channel) 1: Ring (Right channel) Eight Channel AC’97 2.3 Audio Codec Table 37. MX62 PCI Sub System ID Table 38. MX64 PCI Sub Vendor ID Table 39. MX66 Sense Function Select 26 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Stereo Line-In Other: Not supported This field reports the type of output/input peripheral plugged into the jack after sensing 7:0 R Always read as 0 Eight Channel AC’97 2.3 Audio Codec Table 40. MX68 Sense Function Information Table 41. MX6A Sense Detail 27 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Impedance Detect for Pad 21/22 (FO-control 2, 3, and 4) 01: Via 100ohm path 10: Via 2.2K path 11: Via 47K path 00: All path Floating (Default) Software must turn on Surround AMP and turn off SURR-OUT control before detecting Eight Channel AC’97 2.3 Audio Codec Table 42. MX76 GPIO & Interrupt Control 28 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... GPIO1(JD1) Input/Output Status 0: GPIO1 is driven low by/to external device 1: GPIO1 is driven high by/to external device 0 R/W GPIO0(JD0) Input/Output Status 0: GPIO0 is driven low by/to external device 1: GPIO0 is driven high by/to external device Eight Channel AC’97 2.3 Audio Codec Table 43. MX78 GPIO & Interrupt Status 29 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Amplifier at pin 39 and 41 are turned on 4 R/W SURR-OUT 1KΩ Control (SURR-Control) 0: 1KΩ path at pin 39 and 41 are off 1: 1KΩ path at pin 39 and 41 are on (Default) 3:2 Reserved 1 R/W SURR-OUT control 0: Off 1:On (Default) 0 Reserved Eight Channel AC’97 2.3 Audio Codec Table 44. MX7A Miscellaneous Control 30 ALC850 Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC850. The MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The MX7C Vendor ID2 register contains the value 4790h, which is the third character of the Microsoft ID code ...
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... 0.5DVDD IH V 0.5DVDD 0.9DVDD - Typical Maximum 3.3 3.6 5.0 5.5 - +70 +125 Typical Maximum - Dvdd+0.30 0.5DVDD 0.5DVDD 2 0.1DVDD - 100k 130k Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units Units µA µA mA Ω ...
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... Table 50. S/PDIF Output Characteristics Symbol Minimum V 3 Table 51. Cold Reset Symbol Minimum T 1.0 rst_low T 162.8 rst2clk Trst2clk Trst_low Figure 3. Cold Reset Timing 33 Typical Maximum - 19.2 -76.0 +- 0.20 Typical Maximum 3.3 0 0.5 Typical Maximum - - - - Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units kHz kHz dB dB Units V V Units µs ns ...
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... T 162.8 sync2clk Tsync_high Tsync2clk Figure 4. Warm Reset Timing Table 53. AC-Link Clocks Symbol Minimum - T - clk_period - T clk_high T clk_low - T - sync_period T - sync_high T - sync_low 34 Typical Maximum - - - - Typical Maximum 12.288 - 81 750 40.7 40.7 48.0 - 20.8 - 1.3 - 19.5 - Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units µs ns Units MHz kHz µs µs µs ...
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... Table 54. Data Output and Input Timing Symbol Minimum Symbol Minimum t 10 setup t 10 hold Symbol Minimum - - Tsetup Thold V IL Figure 5. Data Output and Input Timing 35 Typical Maximum - 15 Typical Maximum - - - - Typical Maximum - Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units ns Units ns ns Units ns ns ...
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... Trise CLK Trise SYNC Trise DIN Trise DOUT Figure 6. Signal Rise and Fall Timing 36 Typical Maximum - Tfall CLK Tfall SYNC Tfall DIN Tfall DOUT Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units ...
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... SDATA_IN low SYNC BITCLK SDATA-OUT SDATA-IN Eight Channel AC’97 2.3 Audio Codec Table 56. AC-Link Low Power Mode Timing Symbol Minimum T - s2_pdown slot-1 slot-2 Write to MX26 Set PR4 Figure 7. AC-Link Low Power Mode Timing 37 Typical Maximum - 1.0 Ts2_pdown Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units µs ...
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... Eight Channel AC’97 2.3 Audio Codec Table 57. ATE Test Mode Symbol Minimum T 15.0 setup2rst T - off Tsetup2rst Toff Figure 8. ATE Test Mode Timing 1 Codec 2 Codec 55pF 62.5pF 47.5pF 55pF 38 Typical Maximum - - - 25.0 Hi-Z 3 Codec 4 Codec 75pF 85pF 60pF 62.5pF Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units ns ns ...
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... Eight Channel AC’97 2.3 Audio Codec Table 59. S/PDIF Output Minimum Maximum (h) ( (r) (f) Figure 9. S/PDIF Output Rise Time 100 * ® (l) Fall Time 100 * (f) (l) Duty Cycle 100 * (h) (l) 39 Units 90% 50% 10% )% (h) )% (h) )% (h) Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ...
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... Sampling frequency=48kHz; 0dB=1Vrms 10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz 0dB attenuation: Tone and 3D disabled Table 60. Analog Performance Characteristics Minimum - - - - - - - - 19,200 28,800 - - - - - -34.5 40 ALC850 Datasheet Typical Maximum Units 1.6 - Vrms 1.0 - 1.6 - 0.16 - 1.10 - Vrms 1.10 - Vrms 22,000 ...
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... Power Supply Current: VA=5.0V VA=3.3V VD=3.3V Power Down Current: VA=5.0V/3.3V VD=3.3V Vrefout/Vrefout2/Vrefout3 Vrefout Drive Current Eight Channel AC’97 2.3 Audio Codec Minimum Typical Maximum - 1 200 - - - 2. Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet Units - dB +22 KΩ - KΩ - Ω 1000 Ω 7.8/5 4 ...
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... Pulled low ohm resistor. NC: Not Connected or pulled high. ***According to AC’97 ver 2.3, in Primary Mode clock is present at BIT-CLK pin for at least 5 cycles before RESET# is de-asserted, the ALC850 is a consumer of BITCLK. The ALC850 uses external 12.288MHz BITCLK as its clock source. ...
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... Driven SYNC high for specified period without BIT_CLK The AC’97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the ALC850 has reset successfully. 10.4. CD Input For noise cancellation reasons important to pay attention to differential CD input. Below is an example of differential CD input. Eight Channel AC’ ...
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... PR0=0 PRI/J/K=0 Codec Ready 10.7. Test Mode To provide compatibility with AC’97 Rev. 2.2, the ALC850 will float its digital output pins in ATE test mode. Please refer to AC’97 Rev. 2.2, section 9.2, for a detailed description of the test modes. 10.7.1. ATE in Circuit Test Mode SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the ALC850 will drive BIT_CLK, SDATA_IN, EAPD, and S/PDIFO to high impedance ...
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... The Power-Off CD function describes a state where the system has been shut down (digital power is off) When a +5V analog power is supplied the ALC850 will turn on the CD-IN op-amp and output amplifier possible to design a system that can bypass op-amp circuitry and pass CD output directly to the speaker ...
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... The AC’97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the ALC850 has reset successfully CD- 11. Application Circuits Application circuits are for design reference only. System designers are suggested to visit Realtek’s web site to download the latest application circuits ...
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... Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Eight Channel AC’97 2.3 Audio Codec Track ID: JATR-1076-21 Rev. 1.4 ALC850 Datasheet ...
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... Part Number Package ALC850 48-pin LQFP. Standard product ALC850-LF ALC850 + Lead (Pb)-Free package Note: 1. See page 4 for lead (Pb)-free package and version identification. 2. Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek sales representatives or agents. Realtek Semiconductor Corp. ...