hm5225325f-b60 Renesas Electronics Corporation., hm5225325f-b60 Datasheet

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hm5225325f-b60

Manufacturer Part Number
hm5225325f-b60
Description
256m Lvttl Interface Sdram 100 Mhz 1-mword X 64-bit X 4-bank/2-mword X 32-bit X 4-bank Pc/100 Sdram - Hitachi Semiconductor
Manufacturer
Renesas Electronics Corporation.
Datasheet
Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word
HM5225325F is a 256-Mbit SDRAM organized as 2097152-word
are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
Single chip wide bit solution ( 64/ 32)
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Extremely small foot print: 1.27 mm pitch
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 4/8/full page
2 variations of burst sequence
Programmable CAS latency: 2/3
Byte control by DQMB
Package: BGA (BP-108)
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
1-Mword 64-bit 4-bank/2-Mword 32-bit 4-bank
256M LVTTL interface SDRAM
HM5225645F-B60
HM5225325F-B60
PC/100 SDRAM
100 MHz
32-bit
4-bank. All inputs and outputs
64-bit
ADE-203-1014C (Z)
4-bank. The Hitachi
Oct. 1, 1999
Rev. 1.0

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hm5225325f-b60 Summary of contents

Page 1

... HM5225645F-B60 HM5225325F-B60 256M LVTTL interface SDRAM 1-Mword 64-bit 4-bank/2-Mword 32-bit 4-bank Description The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word HM5225325F is a 256-Mbit SDRAM organized as 2097152-word are referred to the rising edge of the clock input packaged in standard 108 bump BGA. ...

Page 2

... HM5225645F-B60, HM5225325F-B60 Refresh cycles: 4096 refresh cycles/ variations of refresh Auto refresh Self refresh Full page burst length capability Sequential burst Burst stop capability Ordering Information Type No. Frequency HM5225645FBP-B60* 100 MHz HM5225325FBP-B60* 100 MHz Note: 66 MHz operation at CAS latency = 2. 2 CAS latency ...

Page 3

... A11 Open CLK MB0 MB1 P DQ6 DQ7 R DQ4 DQ5 T DQ2 DQ3 U DQ0 DQ1 HM5225645F-B60, HM5225325F-B60 108-bump BGA DQ49 DQ48 DQ47 DQ46 DQ33 V DQ51 DQ50 DQ45 DQ44 DQ35 CC DQ53 DQ52 DQ43 DQ42 DQ37 V ...

Page 4

... HM5225645F-B60, HM5225325F-B60 Pin Description (HM5225645F) Pin name Function A0 to A13 Address input DQ0 to DQ63 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command WE Write enable DQMB0 to DQMB7 Byte data mask* CLK Clock input CKE Clock enable V Power supply ...

Page 5

... A11 Open CLK MB0 DQ3 DQ2 NC T DQ1 NC U DQ0 NC HM5225645F-B60, HM5225325F-B60 108-bump BGA DQ24 DQ23 DQ25 DQ22 DQ26 DQ21 DQ27 DQ20 NC ...

Page 6

... HM5225645F-B60, HM5225325F-B60 Pin Description (HM5225325F) Pin name Function A0 to A13 Address input DQ0 to DQ31 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command WE Write enable DQMB0 to DQMB3 Byte data mask* CLK Clock input CKE Clock enable V Power supply ...

Page 7

... Block Diagram (HM5225325F A13 CS RAS CAS WE CLK CKE 64-Mbit SDRAM DQMB 0 to DQMB HM5225645F-B60, HM5225325F-B60 64-Mbit SDRAM 64-Mbit SDRAM 64-Mbit SDRAM 64-Mbit SDRAM 64-Mbit SDRAM ...

Page 8

... HM5225645F-B60, HM5225325F-B60 Power-up Sequence and Initialization Sequence Power up sequence Low CKE, DQMB Low CLK Low CS, DQ Power stabilize Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative Short circuit output current Operating temperature Storage temperature Note: 1 ...

Page 9

... Refresh current I CC5 Self refresh current I CC6 Self refresh current (L-version) I CC6 Input leakage current I LI Output leakage current I LO Output high voltage V Output low voltage V HM5225645F-B60, HM5225325F-B60 = 3 HM5225645F -B60 Min Max — 200 — 220 — 12 — 8 — 64 — 36 — ...

Page 10

... HM5225645F-B60, HM5225325F-B60 DC Characteristics (Tcase = [Tj max = 110 C]), V Parameter Symbol Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power I CC2N down Standby current in non power ...

Page 11

... C I3 Output capacitance (DQ Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition MHz, 1.4 V bias, 200 mV swing. 3. DQMB = V to disable Dout This parameter is sampled and not 100% tested. HM5225645F-B60, HM5225325F-B60 fixed 3.3 V 0.3 V) Min Max 2.5 ...

Page 12

... HM5225645F-B60, HM5225325F-B60 AC Characteristics (Tcase = [Tj max = 110 C]), V HITACHI Parameter Symbol System clock cycle time (CAS latency = 2) t (CAS latency = 3) t CLK high pulse width t CLK low pulse width t Access time from CLK (CAS latency = 2) t (CAS latency = 3) t Data-out hold time ...

Page 13

... Data-in CKE DS DH CES CEH Test Conditions Input and output timing reference levels: 1.5 V Input waveform and output load: See following figures 2.4 V 2.0 V input 0.8 V 0.4 V HM5225645F-B60, HM5225325F-B60 = 1 ns. Reference level for timing of input signals ...

Page 14

... HM5225645F-B60, HM5225325F-B60 Package Dimensions HM5225645FBP Series HM5225325FBP Series (BP-108) Preliminary 14.00 4 C1.2 Pin 1 Index -B- 13.0 108 0. Details of the part A 14 -A- 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) Unit ...

Page 15

... Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 HM5225645F-B60, HM5225325F-B60 Hitachi Asia Pte. Ltd. Hitachi Asia (Hong Kong) Ltd. 16 Collyer Quay #20-00 Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Hitachi Tower ...

Page 16

... HM5225645F-B60, HM5225325F-B60 Revision Record Rev. Date Contents of Modification 0.0 Feb. 1, 1999 Initial issue 0.1 Feb. 19, 1999 Pin arrangement Correct pin No. to JEDEC standard Package dimenssion Correct illustration and indexes 0.2 Apr. 1, 1999 Ordering information Correct error of type No. Programmable CAS latency 2/3 1.0 Oct. 1, 1999 Ordering information ...

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