MK5027N ST Microelectronics, Inc., MK5027N Datasheet
MK5027N
Available stocks
Related parts for MK5027N
MK5027N Summary of contents
Page 1
CMOS FULLY COMPATIBLE WITH BOTH BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND ...
Page 2
MK5027 Table 1: Pin Description. LEGEND: I Input only IO Input/Output OD Open Drain (no internal pull-up) Signal Name Pin(s) DAL<15:00> 2-9 40-47 READ 10 INTR 11 DALI 12 DALO 13 DAS 14 BMO 15 BYTE BUSREL Note: Pin out ...
Page 3
Table 1: Pin Description (continued) Signal Name Pin(s) BM1 16 BUSAKO HOLD 17 BUSRQ ALE 18 AS HLDA 19 Type O/3S Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON). If CSR4<00> BCON = 0, I/O PIN ...
Page 4
MK5027 Table 1: Pin Description (continued) Signal Name Pin( ADR 21 READY 22 RESET 23 TCLK 25 DTR 26 RTS RCLK 27 SYSCLK DSR 30 CTS RD 31 A<23:16> 32-39 VSS-GND 1, 24 VCC 48 ...
Page 5
Figure 2: Possible System Configuration for the MK5027. MK5027 5/19 ...
Page 6
MK5027 Figure 3: MK5027 Simplified Block Diagram. DMA CONTROLLER SYSCLK RCLK RD OPERATIONAL DECRIPTION The SGS-THOMSON Signalling System #7 Sig- nalling Link Controller (MK5027) device is a VLSI product intended for data communication applica- tions requiring SS7 link level control. ...
Page 7
All signal pins on the MK5027 are TTL compat- ible. This has the advantage of making the MK5027 in- dependent of the physical interface. As shown in Figure 2. Iine drivers and receivers are used for electrical- connection to the ...
Page 8
MK5027 Figure 4: MK5027 Buffer Management. CSR 2, CSR3 POINTER TO INITIALIZATION BLOCK INITIALIZATION BLOCK MODE FRAME ADDRESS FIELDS TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINTER XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TEST RECEIVE DESCRIPTOR POINTER STATUS BUFFER ADDRESS ERROR COUNTERS ...
Page 9
SIGNALLING UNIT REPERTOIRE The signal unit repertoire of the MK5027 is shown in Table 1. This set conforms to the 1988 CCITT specification for level 2 of Signalling System #7. The definitions for the symbols for the frame types are: ...
Page 10
MK5027 MK5027 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the above device. This is ...
Page 11
AC TIMING SPECIFICATIONS (Continued +5V 5 percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time RCH 15 RCLK T ...
Page 12
MK5027 AC TIMING SPECIFICATIONS (Continued +5V 5 percent, unless otherwise specified Signal Symbol 42 DAS T Delay from the falling edge of ALE to ADAS the falling edge ...
Page 13
Figure 5A: TTL Output Load Diagram. TEST POINT FROM OUTPUT UNDER TEST C L NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK5027 Serial Link Timing Diagram RCLK RD TCLK TD TIMING MEASUREMENTS ARE ...
Page 14
MK5027 Figure 7: MK5027 Bus Master Timing Diagram (read). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. 14/19 ...
Page 15
Figure 8: MK5027 Bus Master Timing Diagram (write). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. MK5027 15/19 ...
Page 16
MK5027 Figure 9: MK5027 Bus Slave Timing Diagram (read) Figure 10: MK5027 Bus Slave Timing Diagram (write) 16/19 ...
Page 17
DIM. MIN. TYP. MAX. MIN. a1 0.63 b 0.45 b1 0.23 0.31 0.009 b2 1.27 D 62.74 E 15.2 16.68 0.598 e 2.54 e3 58.42 F 14.1 I 4.445 L 3.3 inch MECHANICAL DATA TYP. MAX. 0.025 0.018 0.012 ...
Page 18
MK5027 mm DIM. MIN. TYP. MAX. A 4.20 5.08 A1 0.51 A3 2.29 3.30 B 0.33 0.53 B1 0.66 0.81 C 0.25 D 19.94 20.19 D1 19.05 19.20 D2 17.53 18.54 D3 15.24 E 19.94 20.19 E1 19.05 19.20 E2 ...
Page 19
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...