MK50H25N ST Microelectronics, Inc., MK50H25N Datasheet
MK50H25N
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MK50H25N Summary of contents
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SECTION 1 - FEATURES System clock rate MHz (MK50H25 - 33), 25 MHz (MK50H25 - 25 MHz (MK50H25 - 16). Data rate (MK50H25 - 33 Mbps bursted ...
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MK50H25 DESCRIPTION (Continued) For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. This flexible transparent mode may be easily entered and exited without affecting the X.25 link status or the link state variables kept ...
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PLCC52 PIN CONNECTION (Top view) DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/ MK50H25Q 20 21 MK50H25 47 46 DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 No ...
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MK50H25 TAble 1: PIN DESCRIPTION LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: Pin out for 52 pin PLCC is shown in brackets. SIGNAL NAME PIN(S) TYPE DAL<15:00> 2-9 IO/3S 40-47 [2-10 44-51] ...
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Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE HOLD 17 IO/OD BUSRQ [19] ALE 18 O/3S AS [20] HLDA 19 [21 [22] ADR 21 [23] READY 22 IO/OD [24] If CSR4<00> BCON = 1, I/O PIN 15 ...
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MK50H25 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE RESET 23 [25] TCLK 25 [28] DTR 26 IO RTS [29] RCLK 27 [30] SYSCLK 28 [31 [32] DSR 30 IO CTS [33 [34] A<23:16> 32-39 ...
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Figure 1: Possible System Configuration for thr MK50H25 MEMORY (MULTIPLE DATA BLOCKS) HOST PROCESSOR (68000, 80186, Z8000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL MK50H25 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA ...
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MK50H25 Figure 2: MK50H25 Simplified Block Diagram DMA CONTROLLER SYSCLK RCLK RD 8/62 READY READ DAS CONTROL / STATUS REGISTERS INTERNAL BUS RECEIVER TRANSMITTER FIFO FIFO RECEIVER TRANSMITTER LOOPBACK TEST FIRMWARE ROM MICRO TIMERS CONTROLLER VCC VSS ...
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Functional Blocks Refer to the block diagram in Figure 2. The MK50H25 is primarily initialized and control- led through six 16-bit Control and Status Regis- ters (CSR0 thru CSR5). The CSR’s are accessed through two bus addressable ports, the ...
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MK50H25 FWM of being full (by DMA from TX buffer in shared memory), the transmit FIFO will not inter- rupt the microcontroller until it empties enough to fall below the watermark level. The transmit FIFO also has a selectable Transmit ...
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The MK50H25 will then "look ahead" to the next buffer, and chain ...
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MK50H25 Table A - MK50H25 Command/Response Repertoire FORMAT COMMAND Information Transfer I Supervisory RR RNR REJ * Unnumbered UI SABM DISC * XID TEST Table B - MK50H25 Command/Response Repertoire FORMAT COMMAND Information I Transfer Supervisory RR RNR REJ Unnumbered ...
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Figure 3: MK50H25 Memory Management Structure CSR 2, CSR3 POINTER TO INITIALIZATION BLOCK INITIALIZATION BLOCK MODE FRAME ADDRESS FIELDS TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINTER XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TEST RECEIVE DESCRIPTOR POINTER STATUS BUFFER ADDRESS ERROR COUNTERS ...
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MK50H25 SECTION 4 PROGRAMMING SPECIFICATION This section defines the Control and Status Reg- isters and the memory data structures required to program the MK50H25. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the ...
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Register Data Port (RDP BIT NAME 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the data from ...
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MK50H25 4.1.2 Control and Status Register Definition 4.1.2.1 Control and Status Register 0 (CSR0) RAP<3:1> BIT NAME 15 TDMD 14 STOP 13 DTX 12 DRX ...
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INEA INTERRUPT ENABLE allows the INTR I/O pin to be driven low when the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will be low. If INEA = 0 the INTR ...
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MK50H25 01 RINT 00 0 4.1.2.2 Control and Status Register 1 (CSR1) RAP <3:1> BIT NAME 15 UERR 14 UAV 13 UPARM 12:08 UPRIM 0 1 18/62 ...
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Init: Instructs the MK50H25 to read the Initialization Block from memory. Valid only in the Stopped mode or phase. This should be performed prior to the Start primitive after a bus reset or power-up. 3 Trans: Instructs MK50H25 to ...
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MK50H25 05:04 PPARM PPRIM Disconnect Indication PPARM 0 Remotely Initiated 1 SABM Timeout 2 FRMR Sent the DISC or DM Rcvd Timeout 03:00 PPRIM 20/62 ONLY and is set ...
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Control and Status Register 2 (CSR2) RAP<3:1> BIT NAME 15 CYCLE ...
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MK50H25 07:00 IADR 4.1.2.4 Control and Status Register 3 (CSR3) RAP<3:1> BIT NAME 15:00 IADR 4.1.2.5 Control and Status Register 4 (CSR4) CSR4 allows redefinition of the bus master interface. RAP<3:1> ...
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FWM These bits define the FIFO watermarks. FIFO watermarks prevent the MK50H25 from performing DMA transfers to/from the data buffers until the FIFOs contain a minimum amount of data or space for data. For re- ceive, data will only ...
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MK50H25 01 ACON 00 BCON 4.1.2.6 Control and Status Register 5 (CSR5) CSR5 facilitates control and monitoring of modem controls. RAP<3:1> BIT NAME 15: XEDGE 4 RTSEN 3 DTRD 2 ...
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DSR DATA SET READY is used to control or observe the DSR I/O pin depending on the value of DSRD. If DSRD = 0, this bit be- comes READ ONLY and always equals the current value of the DSR/CTS ...
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MK50H25 4.2 Initialization Block MK50H25 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, portions of the Initialization block are read ...
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Mode Register The Mode Register allows alteration of the MK50H25’s operating parameters IADR + 00 BIT NAME 15:11 MFS<4:0> NUMBER OF FLAGS ...
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MK50H25 04 DTFCS 03 FCSS 02:00 LBACK 4.2.2 Station Addresses The MK50H25 uses the values in Local and Remote Station Address fields of the Initialization Block for filtering received frames and for the address field of transmitted frames. The MK50H25 ...
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Station Address and Control Field Filtering The Local and Remote frame addresses may be either one or two octets according to the EXTA control bit described in the MODE register. If extended address mode filtering is selected, bit zero ...
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MK50H25 Table 3: Address and Control Field Handling By The MK50H25 Receiver In Transparent Mode DACE PROM EXTA EXTAF ...
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Timer/Counters IADR + 06 IADR + 08 IADR + 10 IADR + 12 IADR + 14 There are 5 independent counter-timers. The Host will write the value of these to the Initialization Block. COUNTER DESCRIPTION N1 MAXIMUM FRAME LENGTH. ...
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MK50H25 TP TRANSMIT POLLING TIMER. This scaled timer determines the length of time between polls of the Transmit Descriptor Ring to determine if there is a frame awaiting transmis- sion (i.e. OWNA bit has been set plus other appropriate information ...
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Receive Descriptor Ring Pointer IADR + IADR + 18 BIT NAME 15 RINTD 14:12 RLEN 11 RBSY 10 RBFCS 09 FCSER 08 FCSEN 07:00/15:00 RDRA 4.2.6 Transmit Descriptor Ring Pointer IADR ...
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MK50H25 14:12 TLEN 11 0 10:08 TWD 07:00/15:00 TDRA 4.2.7 XID/TEST Descriptors The XID/TEST Descriptors contain pointers to the buffers used to receive and transmit XID, and TEST frames, as well as buffer lengths. The exact format of these descriptors ...
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Error Counters Seven locations in the Initialization buffer are reserved for use as error counters which the MK50H25 will increment. These counters are intended for use by the host CPU for statistical analysis. The MK50H25 will only increment the ...
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MK50H25 11 UIR 10 FRMRR 09 RADR 08 RPF 07:00 RBADR 4.3.1.2 Receive Message Descriptor 1 (RMD1 BIT NAME 15:01 RBADR 4.3.1.3 Receive Message Descriptor 2 (RMD2 BIT NAME 15:00 BCNT 36/62 ...
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Receive Message Descriptor 3 (RMD3 BIT NAME 15:00 MCNT 4.3.2 Transmit Message Descriptor Entry 4.3.2.1 Transmit Message Descriptor 0 (TMD0 BIT NAME 15 ...
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MK50H25 11 TUI 10 TINTD XPF 07:00 TBADR 4.3.2.2 Transmit Message Descriptor 1 (TMD1 BIT NAME 15:00 TBADR 4.3.2.3 Transmit Message Descriptor 2 (TMD2 BIT NAME 15:00 BCNT 38/62 ...
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Transmit Message Descriptor 3 (TMD3 BIT NAME 15:00 MCNT 4.3.3 Status Buffer 1 5 SBA + 00 SBA + 02 SBA + 04 SBA + 06 SBA + 08 SBA + 10 SBA + 12 ...
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MK50H25 MK50H25 STATUS BUFFER FIELD V(r) V(s) V(A) LOCAL STATE REMOTE STATE PHASE Revision Indicator CURRD<23:0> CURRXD<23:0> 4.4 Detailed Programming Procedures 4.4.1 Initialization (Reading of Initialization Block) The following procedure should be followed to intialize the MK50H25: 1. Setup bus ...
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Active Link Setup The following procedure should be followed to actively establish a link. 1. Issue Connect Request primitive (UPRIM=6) through CSR1. The MK50H25 will attempt to establish a logical link. It does this by sending a SABM/P=1 frame, ...
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MK50H25 4.4.8 Link Reset The following procedure should be followed to reset an established link. 1. Issue a Reset Request primitive (UPRIM=8). 2. Wait for a Reset Confirmation primitive (PPRIM=9) from the MK50H25 (indicating reception of UA frame in response ...
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MK50H25 Internal Self Test The MK50H25 contains an easy to use internal self test designed to test, with a high fault coverage, all of the major blocks of the device except the DMA controller suggested that a ...
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MK50H25 ABSOLUTE MAXIMUM RATINGS Symbol T Temperature Under Bias UB T Storage Temperature stg V Voltage on any pin with respect to ground G P Power Dissipation tot Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 ...
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Figure 5a: TTL Output Load Diagram TEST POINT FROM OUTPUT UNDER TEST C L NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK50H25 Serial Link Timing Diagram RCLK RD TCLK TD TIMING MEASUREMENTS ARE ...
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MK50H25 Figure 7: MK50H25 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed ...
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Figure 7a: MK50H25 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) SYSCLK 64 HOLD HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. This reduced DMA Cycle Time is selected by setting CSR2 ...
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MK50H25 Figure 8: MK50H25 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be ...
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Figure 8a: MK50H25 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) SYSCLK HOLD HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. This Reduced DMA Cycle Time is selected by setting CSR2 bit ...
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MK50H25 Figure 8b: BUS Master BURST Timing (Reduced Cycle - Write SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY 29 DAL0-15 DALO 45 DALI READ BM0,1 56/ ...
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Figure 9: MK50H25 BUS Slave Timing Diagram (Read) SYSCLK CS ADR DAS READY READ (Read) DAL 0-15 NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to be ...
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MK50H25 Figure 10: MK50H25 BUS Slave Timing Diagram (Write) SYSCLK CS ADR DAS READY READ (Write) DAL0-15 NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be ...
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ORDERING INFORMATION MK50H25 Q XX PART# PROTOCOL 50H25 = LAPB SPEED SORT 16 = 16MHz SYSCLK 25 = 25MHz SYSCLK 33 = 33MHz SYSCLK PACKAGE N = Plastic DIP (48 Pins Plastic J-Leaded Cip Carrier (52 Pins) -84Q ...
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MK50H25 mm DIM. MIN. TYP. MAX. a1 0.63 b 0.45 b1 0.23 0.31 0.009 b2 1.27 D 62.74 E 15.2 16.68 0.598 e 2.54 e3 58.42 F 14.1 I 4.445 L 3.3 60/62 inch MIN. TYP. MAX. 0.025 0.018 0.012 ...
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DIM. MIN. TYP. MAX. MIN. A 4.20 5.08 A1 0.51 A3 2.29 3.30 B 0.33 0.53 B1 0.66 0.81 C 0.25 0.01 D 19.94 20.19 D1 19.05 19.20 D2 17.53 18.54 D3 15.24 0.60 E 19.94 20.19 E1 19.05 ...
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MK50H25 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...