mx25l1635dzni-10g Macronix International Co., mx25l1635dzni-10g Datasheet - Page 18

• Manufacturer Part Number: mx25l1635dzni-10g
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

P/N: PM1374
Table 6. Protection Modes
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→sending WRSR instruction code→Status Register
data on SI→ CS# goes high. (see Figure 13)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
-
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware protection
Software protection
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
mode (HPM)
mode (SPM)
Mode
Status register can be written
status register bits cannot be
in (WEL bit is set to "1") and
Status register condition
The SRWD, BP0-BP3 of
the SRWD, BP0-BP3
bits can be changed
changed
18
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP# and SRWD bit status
WP#=1 and SRWD=1
WP#=0, SRWD bit=1
MX25L1635D
be program or erase.
be program or erase.
The protected area
The protected area
REV. 1.7, MAR. 30, 2009
Memory
cannot
cannot