x25640 Intersil Corporation, x25640 Datasheet - Page 5

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x25640

Manufacturer Part Number
x25640
Description
Advanced Spi Serial E2prom With Block Locktm Protection
Manufacturer
Intersil Corporation
Datasheet

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X25640
Operational Notes
The X25640 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read E
Figure 2. Read Status Register Operation Sequence
enter an active state and receive an instruction.
SCK
SO
CS
SI
HIGH IMPEDANCE
2
PROM Array Operation Sequence
SCK
0
SO
CS
SI
1
INSTRUCTION
2
HIGH IMPEDANCE
3
0
4
1
INSTRUCTION
5
2
6
3
7
15 14 13
4
8
5
9
16 BIT ADDRESS
10
6
5
7
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
• CS must come HIGH at the proper clock count in
MSB
enable” latch.
order to start a write cycle.
20 21 22 23 24 25 26 27 28 29 30
8
7
3
9
6
2
10 11 12 13 14
5
1
DATA OUT
4
0
MSB
3
7
2
3089 ILL F09.1
6
1
5
DATA OUT
0
4
3
2
3089 ILL F03.1
1
0

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